117 static inline void mss_qspi_write(const struct mss_qspi_config *cfg,  in mss_qspi_write()  function
129 	mss_qspi_write(s, mask, MSS_QSPI_REG_IEN);  in mss_qspi_enable_ints()
136 	mss_qspi_write(s, mask, MSS_QSPI_REG_IEN);  in mss_qspi_disable_ints()
148 	mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);  in mss_qspi_transmit_x8()
154 			mss_qspi_write(s, ctx->tx_buf[0], MSS_QSPI_REG_TX_DATA);  in mss_qspi_transmit_x8()
169 	mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);  in mss_qspi_transmit_x32()
176 			mss_qspi_write(s, wdata, MSS_QSPI_REG_X4_TX_DATA);  in mss_qspi_transmit_x32()
191 	mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive_x32()
213 	mss_qspi_write(s, rdata, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive_x8()
233 	mss_qspi_write(s, (total_bytes & MSS_QSPI_FRAMESUP_UP_BYTES_MSK),  in mss_qspi_config_frames()
252 	mss_qspi_write(s, skips, MSS_QSPI_REG_FRAMES);  in mss_qspi_config_frames()
330 		mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive()
368 		mss_qspi_write(s, control, MSS_QSPI_REG_CONTROL);  in mss_qspi_clk_gen_set()
404 	mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);  in mss_qspi_hw_mode_set()
419 	mss_qspi_write(cfg, control, MSS_QSPI_REG_CONTROL);  in mss_qspi_release()
440 		mss_qspi_write(cfg, MSS_QSPI_IEN_TXDONE, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
444 		mss_qspi_write(cfg, MSS_QSPI_IEN_RXAVAILABLE, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
449 		mss_qspi_write(cfg, MSS_QSPI_IEN_RXDONE, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
454 		mss_qspi_write(cfg, MSS_QSPI_IEN_TXAVAILABLE, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
458 		mss_qspi_write(cfg, MSS_QSPI_IEN_RXFIFOEMPTY, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
462 		mss_qspi_write(cfg, MSS_QSPI_IEN_TXFIFOFULL, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
565 	mss_qspi_write(cfg, control, MSS_QSPI_REG_CONTROL);  in mss_qspi_init()