111 static inline uint32_t mss_qspi_read(const struct mss_qspi_config *cfg,  in mss_qspi_read()  function
146 	skips = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_transmit_x8()
150 		while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {  in mss_qspi_transmit_x8()
167 	ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_transmit_x32()
171 		while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {  in mss_qspi_transmit_x32()
189 	ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive_x32()
193 		while ((mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY)) {  in mss_qspi_receive_x32()
197 			temp = mss_qspi_read(s, MSS_QSPI_REG_X4_RX_DATA);  in mss_qspi_receive_x32()
211 	rdata = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive_x8()
215 		while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY) {  in mss_qspi_receive_x8()
219 			rdata =  mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);  in mss_qspi_receive_x8()
241 	if (mss_qspi_read(s, MSS_QSPI_REG_CONTROL) & MSS_QSPI_CONTROL_MODE0) {  in mss_qspi_config_frames()
328 		skips = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_receive()
333 			while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) &  in mss_qspi_receive()
338 				rdata =  mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);  in mss_qspi_receive()
349 	uint32_t control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_clk_gen_set()
365 		control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_clk_gen_set()
379 	uint32_t ctrl = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);  in mss_qspi_hw_mode_set()
414 	uint32_t control = mss_qspi_read(cfg, MSS_QSPI_REG_CONTROL);  in mss_qspi_release()
432 	int intfield = mss_qspi_read(cfg, MSS_QSPI_REG_STATUS);  in mss_qspi_interrupt()
433 	int ienfield = mss_qspi_read(cfg, MSS_QSPI_REG_IEN);  in mss_qspi_interrupt()