4  * SPDX-License-Identifier: Apache-2.0
114 	return sys_read32(cfg->base + offset);  in mss_qspi_read()
120 	sys_write32(val, cfg->base + offset);  in mss_qspi_write()
141 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_transmit_x8()
142 	struct mss_qspi_data *data = dev->data;  in mss_qspi_transmit_x8()
143 	struct spi_context *ctx = &data->ctx;  in mss_qspi_transmit_x8()
144 	uint32_t count, skips;  in mss_qspi_transmit_x8()  local
149 	for (count = 0; count < len; ++count) {  in mss_qspi_transmit_x8()
154 			mss_qspi_write(s, ctx->tx_buf[0], MSS_QSPI_REG_TX_DATA);  in mss_qspi_transmit_x8()
162 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_transmit_x32()
163 	struct mss_qspi_data *data = dev->data;  in mss_qspi_transmit_x32()
164 	struct spi_context *ctx = &data->ctx;  in mss_qspi_transmit_x32()
165 	uint32_t count, ctrl, wdata;  in mss_qspi_transmit_x32()  local
170 	for (count = 0; count < len / 4; ++count) {  in mss_qspi_transmit_x32()
175 			wdata = UNALIGNED_GET((uint32_t *)(ctx->tx_buf));  in mss_qspi_transmit_x32()
184 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_receive_x32()
185 	struct mss_qspi_data *data = dev->data;  in mss_qspi_receive_x32()
186 	struct spi_context *ctx = &data->ctx;  in mss_qspi_receive_x32()
187 	uint32_t count, ctrl, temp;  in mss_qspi_receive_x32()  local
192 	for (count = 0; count < len / 4; ++count) {  in mss_qspi_receive_x32()
198 			UNALIGNED_PUT(temp, (uint32_t *)ctx->rx_buf);  in mss_qspi_receive_x32()
206 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_receive_x8()
207 	struct mss_qspi_data *data = dev->data;  in mss_qspi_receive_x8()
208 	struct spi_context *ctx = &data->ctx;  in mss_qspi_receive_x8()
209 	uint32_t rdata, count;  in mss_qspi_receive_x8()  local
214 	for (count = 0; count < len; ++count) {  in mss_qspi_receive_x8()
220 			UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);  in mss_qspi_receive_x8()
230 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_config_frames()
257 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_transmit()
258 	struct mss_qspi_data *data = dev->data;  in mss_qspi_transmit()
259 	struct spi_context *ctx = &data->ctx;  in mss_qspi_transmit()
267 	 * The number of command and data bytes are controlled by the frames register  in mss_qspi_transmit()
269 	 * sequences as below. so configure the cmd and total bytes accordingly.  in mss_qspi_transmit()
270 	 * ---------------------------------------------------------------------  in mss_qspi_transmit()
271 	 * TOTAL BYTES  |  CMD BYTES | What happens                             |  in mss_qspi_transmit()
281 	 *              |            | bytes discarding the receive data and    |  in mss_qspi_transmit()
282 	 *              |            | transmits 6 dummy bytes returning the 6  |  in mss_qspi_transmit()
283 	 *              |            | received bytes and return a single byte  |  in mss_qspi_transmit()
288 	 *              |            | bytes and returning 10 received bytes    |  in mss_qspi_transmit()
291 	if (!ctx->rx_buf) {  in mss_qspi_transmit()
292 		if (total_byte_cnt - cmd_bytes) {  in mss_qspi_transmit()
295 			mss_qspi_transmit_x32(dev, (total_byte_cnt - cmd_bytes));  in mss_qspi_transmit()
311 	const struct mss_qspi_config *s = dev->config;  in mss_qspi_receive()
312 	struct mss_qspi_data *data = dev->data;  in mss_qspi_receive()
313 	struct spi_context *ctx = &data->ctx;  in mss_qspi_receive()
320 	spi_context_update_rx(ctx, 1, ctx->rx_len);  in mss_qspi_receive()
331 		idx = (rd_bytes - (rd_bytes % 4u));  in mss_qspi_receive()
339 				UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);  in mss_qspi_receive()
352 	if (spi_cfg->frequency > s->clock_freq) {  in mss_qspi_clk_gen_set()
353 		speed = s->clock_freq / 2;  in mss_qspi_clk_gen_set()
357 		clkrate = s->clock_freq / (2 * idx);  in mss_qspi_clk_gen_set()
358 		if (clkrate <= spi_cfg->frequency) {  in mss_qspi_clk_gen_set()
370 		return -1;  in mss_qspi_clk_gen_set()
388 		return -1;  in mss_qspi_hw_mode_set()
412 	struct mss_qspi_data *data = dev->data;  in mss_qspi_release()
413 	const struct mss_qspi_config *cfg = dev->config;  in mss_qspi_release()
421 	spi_context_unlock_unconditionally(&data->ctx);  in mss_qspi_release()
428 	const struct mss_qspi_config *cfg = dev->config;  in mss_qspi_interrupt()
429 	struct mss_qspi_data *data = dev->data;  in mss_qspi_interrupt()
430 	struct spi_context *ctx = &data->ctx;  in mss_qspi_interrupt()
469 	const struct mss_qspi_config *cfg = dev->config;  in mss_qspi_configure()
471 	if (spi_cfg->operation & SPI_OP_MODE_SLAVE) {  in mss_qspi_configure()
473 		return -ENOTSUP;  in mss_qspi_configure()
476 	if (spi_cfg->operation & SPI_MODE_LOOP) {  in mss_qspi_configure()
478 		return -ENOTSUP;  in mss_qspi_configure()
481 	if (spi_cfg->operation & (SPI_TRANSFER_LSB) ||  in mss_qspi_configure()
483 		 (spi_cfg->operation & (SPI_LINES_DUAL |  in mss_qspi_configure()
487 		return -ENOTSUP;  in mss_qspi_configure()
492 		return -EINVAL;  in mss_qspi_configure()
506 	const struct mss_qspi_config *config = dev->config;  in mss_qspi_transceive()
507 	struct mss_qspi_data *data = dev->data;  in mss_qspi_transceive()
508 	struct spi_context *ctx = &data->ctx;  in mss_qspi_transceive()
517 	mss_qspi_hw_mode_set(config, spi_cfg->operation);  in mss_qspi_transceive()
553 	const struct mss_qspi_config *cfg = dev->config;  in mss_qspi_init()
554 	struct mss_qspi_data *data = dev->data;  in mss_qspi_init()
558 	cfg->irq_config_func(dev);  in mss_qspi_init()
567 	spi_context_unlock_unconditionally(&data->ctx);  in mss_qspi_init()