Lines Matching +full:hw +full:- +full:rx +full:- +full:buffer +full:- +full:offset
4 * SPDX-License-Identifier: Apache-2.0
86 const struct max32_spi_config *cfg = dev->config; in spi_configure()
87 mxc_spi_regs_t *regs = cfg->regs; in spi_configure()
88 struct max32_spi_data *data = dev->data; in spi_configure()
90 if (spi_context_configured(&data->ctx, config)) { in spi_configure()
94 if (SPI_OP_MODE_GET(config->operation) & SPI_OP_MODE_SLAVE) { in spi_configure()
95 return -ENOTSUP; in spi_configure()
101 int ss_polarity = (config->operation & SPI_CS_ACTIVE_HIGH) ? 1 : 0; in spi_configure()
102 unsigned int spi_speed = (unsigned int)config->frequency; in spi_configure()
109 int cpol = (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) ? 1 : 0; in spi_configure()
110 int cpha = (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) ? 1 : 0; in spi_configure()
125 ret = MXC_SPI_SetDataSize(regs, SPI_WORD_SIZE_GET(config->operation)); in spi_configure()
131 switch (config->operation & SPI_LINES_MASK) { in spi_configure()
139 ret = -ENOTSUP; in spi_configure()
152 data->ctx.config = config; in spi_configure()
159 if (SPI_WORD_SIZE_GET(ctx->config->operation) < 9) { in spi_max32_get_dfs_shift()
168 req->rxCnt = 0; in spi_max32_setup()
169 req->txCnt = 0; in spi_max32_setup()
171 if (spi->ctrl0 & ADI_MAX32_SPI_CTRL_MASTER_MODE) { in spi_max32_setup()
172 MXC_SPI_SetSlave(spi, req->ssIdx); in spi_max32_setup()
175 if (req->rxData && req->rxLen) { in spi_max32_setup()
176 MXC_SETFIELD(spi->ctrl1, MXC_F_SPI_CTRL1_RX_NUM_CHAR, in spi_max32_setup()
177 req->rxLen << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS); in spi_max32_setup()
178 spi->dma |= MXC_F_SPI_DMA_RX_FIFO_EN; in spi_max32_setup()
180 spi->ctrl1 &= ~MXC_F_SPI_CTRL1_RX_NUM_CHAR; in spi_max32_setup()
181 spi->dma &= ~MXC_F_SPI_DMA_RX_FIFO_EN; in spi_max32_setup()
184 if (req->txLen) { in spi_max32_setup()
185 MXC_SETFIELD(spi->ctrl1, MXC_F_SPI_CTRL1_TX_NUM_CHAR, in spi_max32_setup()
186 req->txLen << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS); in spi_max32_setup()
187 spi->dma |= MXC_F_SPI_DMA_TX_FIFO_EN; in spi_max32_setup()
189 spi->ctrl1 &= ~MXC_F_SPI_CTRL1_TX_NUM_CHAR; in spi_max32_setup()
190 spi->dma &= ~MXC_F_SPI_DMA_TX_FIFO_EN; in spi_max32_setup()
193 spi->dma |= (ADI_MAX32_SPI_DMA_TX_FIFO_CLEAR | ADI_MAX32_SPI_DMA_RX_FIFO_CLEAR); in spi_max32_setup()
194 spi->ctrl0 |= MXC_F_SPI_CTRL0_EN; in spi_max32_setup()
203 mxc_spi_req_t *req = &data->req; in spi_max32_transceive_sync()
209 tx_len = req->txLen << dfs_shift; in spi_max32_transceive_sync()
210 rx_len = req->rxLen << dfs_shift; in spi_max32_transceive_sync()
212 remain = tx_len - req->txCnt; in spi_max32_transceive_sync()
214 if (!data->req.txData) { in spi_max32_transceive_sync()
215 req->txCnt += MXC_SPI_WriteTXFIFO(spi, data->dummy, in spi_max32_transceive_sync()
216 MIN(remain, sizeof(data->dummy))); in spi_max32_transceive_sync()
218 req->txCnt += in spi_max32_transceive_sync()
219 MXC_SPI_WriteTXFIFO(spi, &req->txData[req->txCnt], remain); in spi_max32_transceive_sync()
221 if (!(spi->ctrl0 & MXC_F_SPI_CTRL0_START)) { in spi_max32_transceive_sync()
222 spi->ctrl0 |= MXC_F_SPI_CTRL0_START; in spi_max32_transceive_sync()
226 if (req->rxCnt < rx_len) { in spi_max32_transceive_sync()
227 req->rxCnt += MXC_SPI_ReadRXFIFO(spi, &req->rxData[req->rxCnt], in spi_max32_transceive_sync()
228 rx_len - req->rxCnt); in spi_max32_transceive_sync()
230 } while ((req->txCnt < tx_len) || (req->rxCnt < rx_len)); in spi_max32_transceive_sync()
244 const struct max32_spi_config *cfg = dev->config; in spi_max32_transceive()
245 struct max32_spi_data *data = dev->data; in spi_max32_transceive()
246 struct spi_context *ctx = &data->ctx; in spi_max32_transceive()
248 struct spi_rtio *rtio_ctx = data->rtio_ctx; in spi_max32_transceive()
249 struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe; in spi_max32_transceive()
254 MXC_SPI_ClearTXFIFO(cfg->regs); in spi_max32_transceive()
261 switch (sqe->op) { in spi_max32_transceive()
263 len = sqe->rx.buf_len; in spi_max32_transceive()
264 data->req.rxData = sqe->rx.buf; in spi_max32_transceive()
265 data->req.rxLen = sqe->rx.buf_len; in spi_max32_transceive()
266 data->req.txData = NULL; in spi_max32_transceive()
267 data->req.txLen = len >> dfs_shift; in spi_max32_transceive()
270 len = sqe->tx.buf_len; in spi_max32_transceive()
271 data->req.rxLen = 0; in spi_max32_transceive()
272 data->req.rxData = data->dummy; in spi_max32_transceive()
273 data->req.txData = (uint8_t *)sqe->tx.buf; in spi_max32_transceive()
274 data->req.txLen = len >> dfs_shift; in spi_max32_transceive()
277 len = sqe->tiny_tx.buf_len; in spi_max32_transceive()
278 data->req.txData = (uint8_t *)sqe->tiny_tx.buf; in spi_max32_transceive()
279 data->req.rxData = data->dummy; in spi_max32_transceive()
280 data->req.txLen = len >> dfs_shift; in spi_max32_transceive()
281 data->req.rxLen = 0; in spi_max32_transceive()
284 len = sqe->txrx.buf_len; in spi_max32_transceive()
285 data->req.txData = (uint8_t *)sqe->txrx.tx_buf; in spi_max32_transceive()
286 data->req.rxData = sqe->txrx.rx_buf; in spi_max32_transceive()
287 data->req.txLen = len >> dfs_shift; in spi_max32_transceive()
288 data->req.rxLen = len >> dfs_shift; in spi_max32_transceive()
294 data->req.txLen = len >> dfs_shift; in spi_max32_transceive()
295 data->req.txData = (uint8_t *)ctx->tx_buf; in spi_max32_transceive()
296 data->req.rxLen = len >> dfs_shift; in spi_max32_transceive()
297 data->req.rxData = ctx->rx_buf; in spi_max32_transceive()
299 data->req.rxData = ctx->rx_buf; in spi_max32_transceive()
301 data->req.rxLen = len >> dfs_shift; in spi_max32_transceive()
302 if (!data->req.rxData) { in spi_max32_transceive()
303 /* Pass a dummy buffer to HAL if receive buffer is NULL, otherwise in spi_max32_transceive()
306 data->req.rxData = data->dummy; in spi_max32_transceive()
307 data->req.rxLen = 0; in spi_max32_transceive()
310 data->req.spi = cfg->regs; in spi_max32_transceive()
311 data->req.ssIdx = ctx->config->slave; in spi_max32_transceive()
312 data->req.ssDeassert = 0; in spi_max32_transceive()
313 data->req.txCnt = 0; in spi_max32_transceive()
314 data->req.rxCnt = 0; in spi_max32_transceive()
315 spi_max32_setup(cfg->regs, &data->req); in spi_max32_transceive()
317 MXC_SPI_SetTXThreshold(cfg->regs, 1); in spi_max32_transceive()
318 if (data->req.rxLen) { in spi_max32_transceive()
319 MXC_SPI_SetRXThreshold(cfg->regs, 2); in spi_max32_transceive()
320 MXC_SPI_EnableInt(cfg->regs, ADI_MAX32_SPI_INT_EN_RX_THD); in spi_max32_transceive()
322 MXC_SPI_EnableInt(cfg->regs, ADI_MAX32_SPI_INT_EN_TX_THD | ADI_MAX32_SPI_INT_EN_MST_DONE); in spi_max32_transceive()
324 if (!data->req.txData) { in spi_max32_transceive()
325 data->req.txCnt = in spi_max32_transceive()
326 MXC_SPI_WriteTXFIFO(cfg->regs, data->dummy, MIN(len, sizeof(data->dummy))); in spi_max32_transceive()
328 data->req.txCnt = MXC_SPI_WriteTXFIFO(cfg->regs, data->req.txData, len); in spi_max32_transceive()
331 MXC_SPI_StartTransmission(cfg->regs); in spi_max32_transceive()
333 ret = spi_max32_transceive_sync(cfg->regs, data, dfs_shift); in spi_max32_transceive()
335 ret = -EIO; in spi_max32_transceive()
350 struct max32_spi_data *data = dev->data; in transceive()
351 struct spi_context *ctx = &data->ctx; in transceive()
353 const struct max32_spi_config *cfg = dev->config; in transceive()
359 return -ENOTSUP; in transceive()
369 return -EIO; in transceive()
378 MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl); in transceive()
380 /* Assert the CS line if HW control disabled */ in transceive()
384 cfg->regs->ctrl0 = in transceive()
385 (cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) | MXC_F_SPI_CTRL0_SS_CTRL; in transceive()
410 /* Deassert the CS line if hw control disabled */ in transceive()
415 cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL | in transceive()
417 cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN; in transceive()
421 struct spi_rtio *rtio_ctx = data->rtio_ctx; in transceive()
434 const struct device *spi_dev = data->dev; in spi_max32_dma_callback()
435 const struct max32_spi_config *config = spi_dev->config; in spi_max32_dma_callback()
442 if (channel == config->tx_dma.channel) { in spi_max32_dma_callback()
443 data->dma_stat |= SPI_MAX32_DMA_TX_DONE_FLAG; in spi_max32_dma_callback()
444 } else if (channel == config->rx_dma.channel) { in spi_max32_dma_callback()
445 data->dma_stat |= SPI_MAX32_DMA_RX_DONE_FLAG; in spi_max32_dma_callback()
448 if ((data->dma_stat & SPI_MAX32_DMA_DONE_FLAG) == SPI_MAX32_DMA_DONE_FLAG) { in spi_max32_dma_callback()
449 len = spi_context_max_continuous_chunk(&data->ctx); in spi_max32_dma_callback()
450 spi_context_update_tx(&data->ctx, 1, len); in spi_max32_dma_callback()
451 spi_context_update_rx(&data->ctx, 1, len); in spi_max32_dma_callback()
452 spi_context_complete(&data->ctx, spi_dev, status == 0 ? 0 : -EIO); in spi_max32_dma_callback()
460 const struct max32_spi_config *config = dev->config; in spi_max32_tx_dma_load()
461 struct max32_spi_data *data = dev->data; in spi_max32_tx_dma_load()
468 dma_cfg.dma_slot = config->tx_dma.slot; in spi_max32_tx_dma_load()
480 dma_blk.source_address = (uint32_t)data->dummy; in spi_max32_tx_dma_load()
483 ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg); in spi_max32_tx_dma_load()
488 return dma_start(config->tx_dma.dev, config->tx_dma.channel); in spi_max32_tx_dma_load()
495 const struct max32_spi_config *config = dev->config; in spi_max32_rx_dma_load()
496 struct max32_spi_data *data = dev->data; in spi_max32_rx_dma_load()
503 dma_cfg.dma_slot = config->rx_dma.slot; in spi_max32_rx_dma_load()
515 dma_blk.dest_address = (uint32_t)data->dummy; in spi_max32_rx_dma_load()
517 ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg); in spi_max32_rx_dma_load()
519 LOG_ERR("Error configuring Rx DMA (%d)", ret); in spi_max32_rx_dma_load()
522 return dma_start(config->rx_dma.dev, config->rx_dma.channel); in spi_max32_rx_dma_load()
530 const struct max32_spi_config *cfg = dev->config; in transceive_dma()
531 struct max32_spi_data *data = dev->data; in transceive_dma()
532 struct spi_context *ctx = &data->ctx; in transceive_dma()
533 mxc_spi_regs_t *spi = cfg->regs; in transceive_dma()
542 ret = dma_get_status(cfg->tx_dma.dev, cfg->tx_dma.channel, &status); in transceive_dma()
544 ret = ret < 0 ? ret : -EBUSY; in transceive_dma()
548 ret = dma_get_status(cfg->rx_dma.dev, cfg->rx_dma.channel, &status); in transceive_dma()
550 ret = ret < 0 ? ret : -EBUSY; in transceive_dma()
556 ret = -EIO; in transceive_dma()
566 MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl); in transceive_dma()
568 /* Assert the CS line if HW control disabled */ in transceive_dma()
573 MXC_SPI_SetSlave(cfg->regs, ctx->config->slave); in transceive_dma()
576 spi->ctrl0 &= ~(MXC_F_SPI_CTRL0_EN); in transceive_dma()
582 MXC_SETFIELD(spi->ctrl1, MXC_F_SPI_CTRL1_RX_NUM_CHAR, in transceive_dma()
584 spi->dma |= ADI_MAX32_SPI_DMA_RX_FIFO_CLEAR; in transceive_dma()
585 spi->dma |= MXC_F_SPI_DMA_RX_FIFO_EN; in transceive_dma()
586 spi->dma |= ADI_MAX32_SPI_DMA_RX_DMA_EN; in transceive_dma()
589 ret = spi_max32_rx_dma_load(dev, ctx->rx_buf, len, dfs_shift); in transceive_dma()
594 MXC_SETFIELD(spi->ctrl1, MXC_F_SPI_CTRL1_TX_NUM_CHAR, in transceive_dma()
596 spi->dma |= ADI_MAX32_SPI_DMA_TX_FIFO_CLEAR; in transceive_dma()
597 spi->dma |= MXC_F_SPI_DMA_TX_FIFO_EN; in transceive_dma()
598 spi->dma |= ADI_MAX32_SPI_DMA_TX_DMA_EN; in transceive_dma()
601 ret = spi_max32_tx_dma_load(dev, ctx->tx_buf, len, dfs_shift); in transceive_dma()
606 spi->ctrl0 |= MXC_F_SPI_CTRL0_EN; in transceive_dma()
608 data->dma_stat = 0; in transceive_dma()
614 /* Deassert the CS line if hw control disabled */ in transceive_dma()
630 struct max32_spi_data *data = dev->data; in spi_max32_iodev_start()
631 struct spi_rtio *rtio_ctx = data->rtio_ctx; in spi_max32_iodev_start()
632 struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe; in spi_max32_iodev_start()
635 switch (sqe->op) { in spi_max32_iodev_start()
643 spi_max32_iodev_complete(dev, -EINVAL); in spi_max32_iodev_start()
647 spi_max32_iodev_complete(dev, -EIO); in spi_max32_iodev_start()
653 struct max32_spi_data *data = dev->data; in spi_max32_iodev_prepare_start()
654 struct spi_rtio *rtio_ctx = data->rtio_ctx; in spi_max32_iodev_prepare_start()
655 struct spi_dt_spec *spi_dt_spec = rtio_ctx->txn_curr->sqe.iodev->data; in spi_max32_iodev_prepare_start()
656 struct spi_config *spi_config = &spi_dt_spec->config; in spi_max32_iodev_prepare_start()
657 struct max32_spi_config *cfg = (struct max32_spi_config *)dev->config; in spi_max32_iodev_prepare_start()
668 MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl); in spi_max32_iodev_prepare_start()
670 /* Assert the CS line if HW control disabled */ in spi_max32_iodev_prepare_start()
672 spi_context_cs_control(&data->ctx, true); in spi_max32_iodev_prepare_start()
674 cfg->regs->ctrl0 = (cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) | in spi_max32_iodev_prepare_start()
681 struct max32_spi_data *data = dev->data; in spi_max32_iodev_complete()
682 struct spi_rtio *rtio_ctx = data->rtio_ctx; in spi_max32_iodev_complete()
684 if (!status && rtio_ctx->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) { in spi_max32_iodev_complete()
685 rtio_ctx->txn_curr = rtio_txn_next(rtio_ctx->txn_curr); in spi_max32_iodev_complete()
688 struct max32_spi_config *cfg = (struct max32_spi_config *)dev->config; in spi_max32_iodev_complete()
692 spi_context_cs_control(&data->ctx, false); in spi_max32_iodev_complete()
694 cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL | in spi_max32_iodev_complete()
696 cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN; in spi_max32_iodev_complete()
708 struct max32_spi_data *data = dev->data; in api_iodev_submit()
709 struct spi_rtio *rtio_ctx = data->rtio_ctx; in api_iodev_submit()
722 const struct max32_spi_config *cfg = dev->config; in api_transceive()
724 if (cfg->tx_dma.channel != 0xFF && cfg->rx_dma.channel != 0xFF) { in api_transceive()
745 struct spi_context *ctx = &data->ctx; in spi_max32_callback()
746 const struct device *dev = data->dev; in spi_max32_callback()
750 struct spi_rtio *rtio_ctx = data->rtio_ctx; in spi_max32_callback()
752 if (rtio_ctx->txn_head != NULL) { in spi_max32_callback()
753 spi_max32_iodev_complete(data->dev, 0); in spi_max32_callback()
760 if (ctx->asynchronous && ((spi_context_tx_on(ctx) || spi_context_rx_on(ctx)))) { in spi_max32_callback()
761 k_work_submit(&data->async_work); in spi_max32_callback()
763 if (spi_cs_is_gpio(ctx->config)) { in spi_max32_callback()
766 req->spi->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL | in spi_max32_callback()
768 req->spi->ctrl0 |= MXC_F_SPI_CTRL0_EN; in spi_max32_callback()
770 spi_context_complete(ctx, dev, error == E_NO_ERROR ? 0 : -EIO); in spi_max32_callback()
773 spi_context_complete(ctx, dev, error == E_NO_ERROR ? 0 : -EIO); in spi_max32_callback()
781 const struct device *dev = data->dev; in spi_max32_async_work_handler()
786 spi_context_complete(&data->ctx, dev, -EIO); in spi_max32_async_work_handler()
793 const struct max32_spi_config *cfg = dev->config; in spi_max32_isr()
794 struct max32_spi_data *data = dev->data; in spi_max32_isr()
795 mxc_spi_req_t *req = &data->req; in spi_max32_isr()
796 mxc_spi_regs_t *spi = cfg->regs; in spi_max32_isr()
798 uint8_t dfs_shift = spi_max32_get_dfs_shift(&data->ctx); in spi_max32_isr()
803 remain = (req->txLen << dfs_shift) - req->txCnt; in spi_max32_isr()
806 if (!data->req.txData) { in spi_max32_isr()
807 req->txCnt += MXC_SPI_WriteTXFIFO(cfg->regs, data->dummy, in spi_max32_isr()
808 MIN(remain, sizeof(data->dummy))); in spi_max32_isr()
810 req->txCnt += in spi_max32_isr()
811 MXC_SPI_WriteTXFIFO(spi, &req->txData[req->txCnt], remain); in spi_max32_isr()
818 remain = (req->rxLen << dfs_shift) - req->rxCnt; in spi_max32_isr()
820 req->rxCnt += MXC_SPI_ReadRXFIFO(spi, &req->rxData[req->rxCnt], remain); in spi_max32_isr()
821 remain = (req->rxLen << dfs_shift) - req->rxCnt; in spi_max32_isr()
831 if ((req->txLen == req->txCnt) && (req->rxLen == req->rxCnt)) { in spi_max32_isr()
843 struct max32_spi_data *data = dev->data; in api_release()
846 if (!spi_context_configured(&data->ctx, config)) { in api_release()
847 return -EINVAL; in api_release()
850 spi_context_unlock_unconditionally(&data->ctx); in api_release()
857 const struct max32_spi_config *const cfg = dev->config; in spi_max32_init()
858 mxc_spi_regs_t *regs = cfg->regs; in spi_max32_init()
859 struct max32_spi_data *data = dev->data; in spi_max32_init()
861 if (!device_is_ready(cfg->clock)) { in spi_max32_init()
862 return -ENODEV; in spi_max32_init()
867 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk); in spi_max32_init()
872 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT); in spi_max32_init()
877 ret = spi_context_cs_configure_all(&data->ctx); in spi_max32_init()
882 data->dev = dev; in spi_max32_init()
885 spi_rtio_init(data->rtio_ctx, dev); in spi_max32_init()
889 cfg->irq_config_func(dev); in spi_max32_init()
891 k_work_init(&data->async_work, spi_max32_async_work_handler); in spi_max32_init()
895 spi_context_unlock_unconditionally(&data->ctx); in spi_max32_init()
941 .rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx), \
942 .rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel), \
943 .rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
960 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \