Lines Matching +full:source +full:- +full:dir
4 * SPDX-License-Identifier: Apache-2.0
61 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_config()
65 sclk_div = (cfg->f_sys / (config->frequency << 1)) - 1; in spi_config()
66 sys_clear_bits(SPI_TIMIN(cfg->base), TIMIN_SCLK_DIV_MSK); in spi_config()
67 sys_set_bits(SPI_TIMIN(cfg->base), sclk_div); in spi_config()
70 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_SLVMODE_MSK); in spi_config()
73 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_MERGE_MSK); in spi_config()
76 data_len = SPI_WORD_SIZE_GET(config->operation) - 1; in spi_config()
77 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_LEN_MSK); in spi_config()
78 sys_set_bits(SPI_TFMAT(cfg->base), (data_len << TFMAT_DATA_LEN_OFFSET)); in spi_config()
81 if (config->operation & SPI_MODE_CPHA) { in spi_config()
82 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
84 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
87 if (config->operation & SPI_MODE_CPOL) { in spi_config()
88 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
90 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
94 if (config->operation & SPI_TRANSFER_LSB) { in spi_config()
95 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
97 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
101 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_THRES_MSK); in spi_config()
102 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_RX_THRES_MSK); in spi_config()
104 sys_set_bits(SPI_CTRL(cfg->base), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET); in spi_config()
105 sys_set_bits(SPI_CTRL(cfg->base), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET); in spi_config()
112 struct spi_atcspi200_data * const data = dev->data; in spi_transfer()
113 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_transfer()
114 struct spi_context *ctx = &data->ctx; in spi_transfer()
117 if (data->chunk_len != 0) { in spi_transfer()
118 data_len = data->chunk_len - 1; in spi_transfer()
124 return -EINVAL; in spi_transfer()
127 data->tx_cnt = 0; in spi_transfer()
146 sys_write32(tctrl, SPI_TCTRL(cfg->base)); in spi_transfer()
149 sys_write32(int_msk, SPI_INTEN(cfg->base)); in spi_transfer()
152 sys_write32(0, SPI_CMD(cfg->base)); in spi_transfer()
161 struct spi_atcspi200_data * const data = dev->data; in configure()
162 struct spi_context *ctx = &(data->ctx); in configure()
169 if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) { in configure()
171 dev->name); in configure()
172 return -EINVAL; in configure()
175 if (config->operation & SPI_MODE_LOOP) { in configure()
177 return -EINVAL; in configure()
180 if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { in configure()
182 return -EINVAL; in configure()
185 ctx->config = config; in configure()
201 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_tx_dma_enable()
203 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_enable()
208 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_tx_dma_disable()
210 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_disable()
215 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_rx_dma_enable()
217 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_enable()
222 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_rx_dma_disable()
224 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_disable()
229 struct spi_atcspi200_data *data = dev->data; in spi_dma_move_buffers()
230 struct spi_context *ctx = &data->ctx; in spi_dma_move_buffers()
233 data->dma_rx.dma_blk_cfg.next_block = NULL; in spi_dma_move_buffers()
234 data->dma_tx.dma_blk_cfg.next_block = NULL; in spi_dma_move_buffers()
257 struct spi_atcspi200_data *data = spi_dev->data; in dma_rx_callback()
258 struct spi_context *ctx = &data->ctx; in dma_rx_callback()
261 dma_stop(data->dma_rx.dma_dev, data->dma_rx.channel); in dma_rx_callback()
269 error = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel); in dma_rx_callback()
278 struct spi_atcspi200_data *data = spi_dev->data; in dma_tx_callback()
279 struct spi_context *ctx = &data->ctx; in dma_tx_callback()
282 dma_stop(data->dma_tx.dma_dev, data->dma_tx.channel); in dma_tx_callback()
290 error = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in dma_tx_callback()
303 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_dma_tx_load()
304 struct spi_atcspi200_data *data = dev->data; in spi_dma_tx_load()
305 struct spi_context *ctx = &data->ctx; in spi_dma_tx_load()
309 memset(&data->dma_tx.dma_blk_cfg, 0, sizeof(struct dma_block_config)); in spi_dma_tx_load()
311 if (ctx->current_tx->len > data->chunk_len) { in spi_dma_tx_load()
312 data->dma_tx.dma_blk_cfg.block_size = data->chunk_len / in spi_dma_tx_load()
313 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
315 data->dma_tx.dma_blk_cfg.block_size = ctx->current_tx->len / in spi_dma_tx_load()
316 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
319 /* tx direction has memory as source and periph as dest. */ in spi_dma_tx_load()
320 if (ctx->current_tx->buf == NULL) { in spi_dma_tx_load()
323 data->dma_tx.dma_blk_cfg.source_address = (uintptr_t)&dummy_rx_tx_buffer; in spi_dma_tx_load()
324 data->dma_tx.dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
326 data->dma_tx.dma_blk_cfg.source_address = (uintptr_t)ctx->current_tx->buf; in spi_dma_tx_load()
327 if (data->dma_tx.src_addr_increment) { in spi_dma_tx_load()
328 data->dma_tx.dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_tx_load()
330 data->dma_tx.dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
334 dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3; in spi_dma_tx_load()
335 remain_len = data->chunk_len - ctx->current_tx->len; in spi_dma_tx_load()
336 spi_context_update_tx(ctx, dfs, ctx->current_tx->len); in spi_dma_tx_load()
338 data->dma_tx.dma_blk_cfg.dest_address = (uint32_t)SPI_DATA(cfg->base); in spi_dma_tx_load()
340 if (data->dma_tx.dst_addr_increment) { in spi_dma_tx_load()
341 data->dma_tx.dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_tx_load()
343 data->dma_tx.dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
347 data->dma_tx.dma_cfg.head_block = &data->dma_tx.dma_blk_cfg; in spi_dma_tx_load()
348 data->dma_tx.dma_cfg.head_block->next_block = NULL; in spi_dma_tx_load()
350 data->dma_tx.dma_cfg.user_data = (void *)dev; in spi_dma_tx_load()
352 if (data->dma_tx.dma_cfg.source_chaining_en) { in spi_dma_tx_load()
353 data->dma_tx.dma_cfg.block_count = ctx->tx_count; in spi_dma_tx_load()
354 data->dma_tx.dma_cfg.dma_callback = NULL; in spi_dma_tx_load()
355 data->dma_tx.block_idx = 0; in spi_dma_tx_load()
356 struct dma_block_config *blk_cfg = &data->dma_tx.dma_blk_cfg; in spi_dma_tx_load()
357 const struct spi_buf *current_tx = ctx->current_tx; in spi_dma_tx_load()
362 next_blk_cfg = &data->dma_tx.chain_block[data->dma_tx.block_idx]; in spi_dma_tx_load()
363 data->dma_tx.block_idx += 1; in spi_dma_tx_load()
365 blk_cfg->next_block = next_blk_cfg; in spi_dma_tx_load()
366 current_tx = ctx->current_tx; in spi_dma_tx_load()
368 next_blk_cfg->block_size = current_tx->len / in spi_dma_tx_load()
369 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
371 /* tx direction has memory as source and periph as dest. */ in spi_dma_tx_load()
372 if (current_tx->buf == NULL) { in spi_dma_tx_load()
375 next_blk_cfg->source_address = (uintptr_t)&dummy_rx_tx_buffer; in spi_dma_tx_load()
376 next_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
378 next_blk_cfg->source_address = (uintptr_t)current_tx->buf; in spi_dma_tx_load()
379 if (data->dma_tx.src_addr_increment) { in spi_dma_tx_load()
380 next_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_tx_load()
382 next_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
386 next_blk_cfg->dest_address = (uint32_t)SPI_DATA(cfg->base); in spi_dma_tx_load()
388 if (data->dma_tx.dst_addr_increment) { in spi_dma_tx_load()
389 next_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_tx_load()
391 next_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_tx_load()
395 next_blk_cfg->next_block = NULL; in spi_dma_tx_load()
396 remain_len -= ctx->current_tx->len; in spi_dma_tx_load()
397 spi_context_update_tx(ctx, dfs, ctx->current_tx->len); in spi_dma_tx_load()
401 data->dma_tx.dma_blk_cfg.next_block = NULL; in spi_dma_tx_load()
402 data->dma_tx.dma_cfg.block_count = 1; in spi_dma_tx_load()
403 data->dma_tx.dma_cfg.dma_callback = dma_tx_callback; in spi_dma_tx_load()
406 /* pass our client origin to the dma: data->dma_tx.dma_channel */ in spi_dma_tx_load()
407 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.channel, in spi_dma_tx_load()
408 &data->dma_tx.dma_cfg); in spi_dma_tx_load()
411 data->dma_tx.block_idx = 0; in spi_dma_tx_load()
412 data->dma_tx.dma_blk_cfg.next_block = NULL; in spi_dma_tx_load()
421 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_dma_rx_load()
422 struct spi_atcspi200_data *data = dev->data; in spi_dma_rx_load()
423 struct spi_context *ctx = &data->ctx; in spi_dma_rx_load()
427 memset(&data->dma_rx.dma_blk_cfg, 0, sizeof(struct dma_block_config)); in spi_dma_rx_load()
429 if (ctx->current_rx->len > data->chunk_len) { in spi_dma_rx_load()
430 data->dma_rx.dma_blk_cfg.block_size = data->chunk_len / in spi_dma_rx_load()
431 data->dma_rx.dma_cfg.dest_data_size; in spi_dma_rx_load()
433 data->dma_rx.dma_blk_cfg.block_size = ctx->current_rx->len / in spi_dma_rx_load()
434 data->dma_rx.dma_cfg.dest_data_size; in spi_dma_rx_load()
437 /* rx direction has periph as source and mem as dest. */ in spi_dma_rx_load()
438 if (ctx->current_rx->buf == NULL) { in spi_dma_rx_load()
440 data->dma_rx.dma_blk_cfg.dest_address = (uintptr_t)&dummy_rx_tx_buffer; in spi_dma_rx_load()
441 data->dma_rx.dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
443 data->dma_rx.dma_blk_cfg.dest_address = (uintptr_t)ctx->current_rx->buf; in spi_dma_rx_load()
444 if (data->dma_rx.dst_addr_increment) { in spi_dma_rx_load()
445 data->dma_rx.dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_rx_load()
447 data->dma_rx.dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
451 dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3; in spi_dma_rx_load()
452 remain_len = data->chunk_len - ctx->current_rx->len; in spi_dma_rx_load()
453 spi_context_update_rx(ctx, dfs, ctx->current_rx->len); in spi_dma_rx_load()
455 data->dma_rx.dma_blk_cfg.source_address = (uint32_t)SPI_DATA(cfg->base); in spi_dma_rx_load()
457 if (data->dma_rx.src_addr_increment) { in spi_dma_rx_load()
458 data->dma_rx.dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_rx_load()
460 data->dma_rx.dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
463 data->dma_rx.dma_cfg.head_block = &data->dma_rx.dma_blk_cfg; in spi_dma_rx_load()
464 data->dma_rx.dma_cfg.head_block->next_block = NULL; in spi_dma_rx_load()
465 data->dma_rx.dma_cfg.user_data = (void *)dev; in spi_dma_rx_load()
467 if (data->dma_rx.dma_cfg.source_chaining_en) { in spi_dma_rx_load()
468 data->dma_rx.dma_cfg.block_count = ctx->rx_count; in spi_dma_rx_load()
469 data->dma_rx.dma_cfg.dma_callback = NULL; in spi_dma_rx_load()
470 data->dma_rx.block_idx = 0; in spi_dma_rx_load()
471 struct dma_block_config *blk_cfg = &data->dma_rx.dma_blk_cfg; in spi_dma_rx_load()
472 const struct spi_buf *current_rx = ctx->current_rx; in spi_dma_rx_load()
477 next_blk_cfg = &data->dma_rx.chain_block[data->dma_rx.block_idx]; in spi_dma_rx_load()
478 data->dma_rx.block_idx += 1; in spi_dma_rx_load()
480 blk_cfg->next_block = next_blk_cfg; in spi_dma_rx_load()
481 current_rx = ctx->current_rx; in spi_dma_rx_load()
483 next_blk_cfg->block_size = current_rx->len / in spi_dma_rx_load()
484 data->dma_rx.dma_cfg.dest_data_size; in spi_dma_rx_load()
486 /* rx direction has periph as source and mem as dest. */ in spi_dma_rx_load()
487 if (current_rx->buf == NULL) { in spi_dma_rx_load()
489 next_blk_cfg->dest_address = (uintptr_t)&dummy_rx_tx_buffer; in spi_dma_rx_load()
490 next_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
492 next_blk_cfg->dest_address = (uintptr_t)current_rx->buf; in spi_dma_rx_load()
493 if (data->dma_rx.dst_addr_increment) { in spi_dma_rx_load()
494 next_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_rx_load()
496 next_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
500 next_blk_cfg->source_address = (uint32_t)SPI_DATA(cfg->base); in spi_dma_rx_load()
502 if (data->dma_rx.src_addr_increment) { in spi_dma_rx_load()
503 next_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_dma_rx_load()
505 next_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_dma_rx_load()
509 next_blk_cfg->next_block = NULL; in spi_dma_rx_load()
510 remain_len -= ctx->current_rx->len; in spi_dma_rx_load()
511 spi_context_update_rx(ctx, dfs, ctx->current_rx->len); in spi_dma_rx_load()
514 data->dma_rx.dma_blk_cfg.next_block = NULL; in spi_dma_rx_load()
515 data->dma_rx.dma_cfg.block_count = 1; in spi_dma_rx_load()
516 data->dma_rx.dma_cfg.dma_callback = dma_rx_callback; in spi_dma_rx_load()
519 /* pass our client origin to the dma: data->dma_rx.channel */ in spi_dma_rx_load()
520 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.channel, in spi_dma_rx_load()
521 &data->dma_rx.dma_cfg); in spi_dma_rx_load()
524 data->dma_rx.block_idx = 0; in spi_dma_rx_load()
525 data->dma_rx.dma_blk_cfg.next_block = NULL; in spi_dma_rx_load()
534 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_transfer_dma()
535 struct spi_atcspi200_data * const data = dev->data; in spi_transfer_dma()
536 struct spi_context *ctx = &data->ctx; in spi_transfer_dma()
540 data_len = data->chunk_len - 1; in spi_transfer_dma()
542 return -EINVAL; in spi_transfer_dma()
563 sys_write32(tctrl, SPI_TCTRL(cfg->base)); in spi_transfer_dma()
566 sys_clear_bits(SPI_TIMIN(cfg->base), 0xff); in spi_transfer_dma()
569 sys_write32(IEN_END_MSK, SPI_INTEN(cfg->base)); in spi_transfer_dma()
578 sys_write32(0, SPI_CMD(cfg->base)); in spi_transfer_dma()
582 error = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel); in spi_transfer_dma()
589 error = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel); in spi_transfer_dma()
607 const struct spi_atcspi200_cfg * const cfg = dev->config; in transceive()
608 struct spi_atcspi200_data * const data = dev->data; in transceive()
609 struct spi_context *ctx = &data->ctx; in transceive()
616 data->busy = true; in transceive()
618 dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3; in transceive()
622 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_FIFO_RST_MSK); in transceive()
623 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_FIFO_RST_MSK); in transceive()
636 data->chunk_len = chunk_len; in transceive()
639 if ((data->dma_tx.dma_dev != NULL) && (data->dma_rx.dma_dev != NULL)) { in transceive()
690 struct spi_atcspi200_data * const data = dev->data; in spi_atcspi200_release()
692 if (data->busy) { in spi_atcspi200_release()
693 return -EBUSY; in spi_atcspi200_release()
696 spi_context_unlock_unconditionally(&data->ctx); in spi_atcspi200_release()
703 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_atcspi200_init()
704 struct spi_atcspi200_data * const data = dev->data; in spi_atcspi200_init()
708 if (cfg->xip) { in spi_atcspi200_init()
709 return -EINVAL; in spi_atcspi200_init()
712 spi_context_unlock_unconditionally(&data->ctx); in spi_atcspi200_init()
715 if (!data->dma_tx.dma_dev) { in spi_atcspi200_init()
717 return -ENODEV; in spi_atcspi200_init()
720 if (!data->dma_rx.dma_dev) { in spi_atcspi200_init()
722 return -ENODEV; in spi_atcspi200_init()
727 data->tx_fifo_size = TX_FIFO_SIZE(cfg->base); in spi_atcspi200_init()
728 data->rx_fifo_size = RX_FIFO_SIZE(cfg->base); in spi_atcspi200_init()
730 cfg->cfg_func(); in spi_atcspi200_init()
732 irq_enable(cfg->irq_num); in spi_atcspi200_init()
734 err = spi_context_cs_configure_all(&data->ctx); in spi_atcspi200_init()
756 const struct spi_atcspi200_cfg * const cfg = dev->config; in spi_atcspi200_irq_handler()
757 struct spi_atcspi200_data * const data = dev->data; in spi_atcspi200_irq_handler()
758 struct spi_context *ctx = &data->ctx; in spi_atcspi200_irq_handler()
764 intr_status = sys_read32(SPI_INTST(cfg->base)); in spi_atcspi200_irq_handler()
765 dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3; in spi_atcspi200_irq_handler()
770 spi_status = sys_read32(SPI_STAT(cfg->base)); in spi_atcspi200_irq_handler()
771 cur_tx_fifo_num = GET_TX_NUM(cfg->base); in spi_atcspi200_irq_handler()
773 tx_num = data->tx_fifo_size - cur_tx_fifo_num; in spi_atcspi200_irq_handler()
775 for (i = tx_num; i > 0; i--) { in spi_atcspi200_irq_handler()
777 if (data->tx_cnt >= data->chunk_len) { in spi_atcspi200_irq_handler()
781 sys_clear_bits(SPI_INTEN(cfg->base), IEN_TX_FIFO_MSK); in spi_atcspi200_irq_handler()
789 tx_data = *ctx->tx_buf; in spi_atcspi200_irq_handler()
792 tx_data = *(uint16_t *)ctx->tx_buf; in spi_atcspi200_irq_handler()
799 sys_clear_bits(SPI_INTEN(cfg->base), IEN_TX_FIFO_MSK); in spi_atcspi200_irq_handler()
803 sys_write32(tx_data, SPI_DATA(cfg->base)); in spi_atcspi200_irq_handler()
807 data->tx_cnt++; in spi_atcspi200_irq_handler()
809 sys_write32(INTST_TX_FIFO_INT_MSK, SPI_INTST(cfg->base)); in spi_atcspi200_irq_handler()
814 cur_rx_fifo_num = GET_RX_NUM(cfg->base); in spi_atcspi200_irq_handler()
816 for (i = cur_rx_fifo_num; i > 0; i--) { in spi_atcspi200_irq_handler()
818 rx_data = sys_read32(SPI_DATA(cfg->base)); in spi_atcspi200_irq_handler()
824 *ctx->rx_buf = rx_data; in spi_atcspi200_irq_handler()
827 *(uint16_t *)ctx->rx_buf = rx_data; in spi_atcspi200_irq_handler()
832 sys_clear_bits(SPI_INTEN(cfg->base), IEN_RX_FIFO_MSK); in spi_atcspi200_irq_handler()
837 sys_write32(INTST_RX_FIFO_INT_MSK, SPI_INTST(cfg->base)); in spi_atcspi200_irq_handler()
843 sys_write32(INTST_END_INT_MSK, SPI_INTST(cfg->base)); in spi_atcspi200_irq_handler()
846 sys_write32(0, SPI_INTEN(cfg->base)); in spi_atcspi200_irq_handler()
849 if ((data->dma_tx.dma_dev != NULL) && data->dma_tx.dma_cfg.source_chaining_en) { in spi_atcspi200_irq_handler()
852 dma_stop(data->dma_tx.dma_dev, data->dma_tx.channel); in spi_atcspi200_irq_handler()
853 data->dma_tx.block_idx = 0; in spi_atcspi200_irq_handler()
854 data->dma_tx.dma_blk_cfg.next_block = NULL; in spi_atcspi200_irq_handler()
857 if ((data->dma_rx.dma_dev != NULL) && data->dma_rx.dma_cfg.source_chaining_en) { in spi_atcspi200_irq_handler()
860 dma_stop(data->dma_rx.dma_dev, data->dma_rx.channel); in spi_atcspi200_irq_handler()
861 data->dma_rx.block_idx = 0; in spi_atcspi200_irq_handler()
862 data->dma_rx.dma_blk_cfg.next_block = NULL; in spi_atcspi200_irq_handler()
866 data->busy = false; in spi_atcspi200_irq_handler()
882 #define DMA_CHANNEL_CONFIG(id, dir) \ argument
883 DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config)
885 #define SPI_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \ argument
886 .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)), \
888 DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
891 DT_INST_DMAS_CELL_BY_NAME(index, dir, slot), \
893 DMA_CHANNEL_CONFIG(index, dir)), \
898 DMA_CHANNEL_CONFIG(index, dir) \
902 DMA_CHANNEL_CONFIG(index, dir) \
907 DMA_CHANNEL_CONFIG(index, dir) \
910 index, dir), chain_transfer), \
912 index, dir), chain_transfer), \
916 DMA_CHANNEL_CONFIG(index, dir) \
920 DMA_CHANNEL_CONFIG(index, dir) \
923 #define SPI_DMA_CHANNEL(id, dir, DIR, src, dest) \ argument
924 .dma_##dir = { \
925 COND_CODE_1(DT_INST_DMAS_HAS_NAME(id, dir), \
926 (SPI_DMA_CHANNEL_INIT(id, dir, DIR, src, dest)), \
931 #define SPI_DMA_CHANNEL(id, dir, DIR, src, dest) argument