83 	get_uart(dev)->cr |=  PL011_CR_UARTEN;  in pl011_enable()
88 	get_uart(dev)->cr &= ~PL011_CR_UARTEN;  in pl011_disable()
93 	get_uart(dev)->lcr_h |= PL011_LCRH_FEN;  in pl011_enable_fifo()
98 	get_uart(dev)->lcr_h &= ~PL011_LCRH_FEN;  in pl011_disable_fifo()
104 		get_uart(dev)->cr |= PL011_CR_RTSEn;  in pl011_set_flow_control()
106 		get_uart(dev)->cr &= ~PL011_CR_RTSEn;  in pl011_set_flow_control()
109 		get_uart(dev)->cr |= PL011_CR_CTSEn;  in pl011_set_flow_control()
111 		get_uart(dev)->cr &= ~PL011_CR_CTSEn;  in pl011_set_flow_control()
131 	get_uart(dev)->ibrd = bauddiv >> PL011_FBRD_WIDTH;  in pl011_set_baudrate()
132 	get_uart(dev)->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);  in pl011_set_baudrate()
140 	get_uart(dev)->lcr_h = get_uart(dev)->lcr_h;  in pl011_set_baudrate()
150 	    (!(get_uart(dev)->cr & PL011_CR_UARTEN) || !(get_uart(dev)->cr & PL011_CR_RXE))) {  in pl011_is_readable()
154 	return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U;  in pl011_is_readable()
164 	*c = (unsigned char)get_uart(dev)->dr;  in pl011_poll_in()
166 	return get_uart(dev)->rsr & PL011_RSR_ERROR_MASK;  in pl011_poll_in()
173 	while (get_uart(dev)->fr & PL011_FR_TXFF) {  in pl011_poll_out()
178 	get_uart(dev)->dr = (uint32_t)c;  in pl011_poll_out()
185 	if (get_uart(dev)->rsr & PL011_RSR_ECR_OE) {  in pl011_err_check()
189 	if (get_uart(dev)->rsr & PL011_RSR_ECR_BE) {  in pl011_err_check()
193 	if (get_uart(dev)->rsr & PL011_RSR_ECR_PE) {  in pl011_err_check()
197 	if (get_uart(dev)->rsr & PL011_RSR_ECR_FE) {  in pl011_err_check()
221 	lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK | PL011_LCRH_STP2);  in pl011_runtime_configure_internal()
283 	get_uart(dev)->lcr_h = lcrh;  in pl011_runtime_configure_internal()
322 	while (!(get_uart(dev)->fr & PL011_FR_TXFF) && (len - num_tx > 0)) {  in pl011_fifo_fill()
323 		get_uart(dev)->dr = tx_data[num_tx++];  in pl011_fifo_fill()
333 	while ((len - num_rx > 0) && !(get_uart(dev)->fr & PL011_FR_RXFE)) {  in pl011_fifo_read()
334 		rx_data[num_rx++] = get_uart(dev)->dr;  in pl011_fifo_read()
344 	get_uart(dev)->imsc |= PL011_IMSC_TXIM;  in pl011_irq_tx_enable()
368 	get_uart(dev)->imsc &= ~PL011_IMSC_TXIM;  in pl011_irq_tx_disable()
374 	return ((get_uart(dev)->fr & PL011_FR_BUSY) == 0);  in pl011_irq_tx_complete()
381 	if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_TXE)) {  in pl011_irq_tx_ready()
385 	return ((get_uart(dev)->imsc & PL011_IMSC_TXIM) &&  in pl011_irq_tx_ready()
387 		(get_uart(dev)->ris & PL011_RIS_TXRIS || get_uart(dev)->fr & PL011_FR_TXFE));  in pl011_irq_tx_ready()
392 	get_uart(dev)->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;  in pl011_irq_rx_enable()
397 	get_uart(dev)->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);  in pl011_irq_rx_disable()
404 	if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_RXE)) {  in pl011_irq_rx_ready()
408 	return ((get_uart(dev)->imsc & PL011_IMSC_RXIM) &&  in pl011_irq_rx_ready()
409 		(!(get_uart(dev)->fr & PL011_FR_RXFE)));  in pl011_irq_rx_ready()
415 	get_uart(dev)->imsc |= PL011_IMSC_ERROR_MASK;  in pl011_irq_err_enable()
420 	get_uart(dev)->imsc &= ~PL011_IMSC_ERROR_MASK;  in pl011_irq_err_disable()
526 		get_uart(dev)->ifls = FIELD_PREP(PL011_IFLS_TXIFLSEL_M, TXIFLSEL_1_8_FULL)  in pl011_init()
533 	get_uart(dev)->imsc = 0U;  in pl011_init()
534 	get_uart(dev)->icr = PL011_IMSC_MASK_ALL;  in pl011_init()
537 		get_uart(dev)->dmacr = 0U;  in pl011_init()
539 		get_uart(dev)->cr &= ~PL011_CR_SIREN;  in pl011_init()
540 		get_uart(dev)->cr |= PL011_CR_RXE | PL011_CR_TXE;  in pl011_init()