Lines Matching +full:left +full:- +full:shifted
6 * SPDX-License-Identifier: Apache-2.0
83 get_uart(dev)->cr |= PL011_CR_UARTEN; in pl011_enable()
88 get_uart(dev)->cr &= ~PL011_CR_UARTEN; in pl011_disable()
93 get_uart(dev)->lcr_h |= PL011_LCRH_FEN; in pl011_enable_fifo()
98 get_uart(dev)->lcr_h &= ~PL011_LCRH_FEN; in pl011_disable_fifo()
104 get_uart(dev)->cr |= PL011_CR_RTSEn; in pl011_set_flow_control()
106 get_uart(dev)->cr &= ~PL011_CR_RTSEn; in pl011_set_flow_control()
109 get_uart(dev)->cr |= PL011_CR_CTSEn; in pl011_set_flow_control()
111 get_uart(dev)->cr &= ~PL011_CR_CTSEn; in pl011_set_flow_control()
118 /* Avoiding float calculations, bauddiv is left shifted by 6 */ in pl011_set_baudrate()
128 return -EINVAL; in pl011_set_baudrate()
131 get_uart(dev)->ibrd = bauddiv >> PL011_FBRD_WIDTH; in pl011_set_baudrate()
132 get_uart(dev)->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u); in pl011_set_baudrate()
138 * ARM DDI 0183F, Pg 3-13 in pl011_set_baudrate()
140 get_uart(dev)->lcr_h = get_uart(dev)->lcr_h; in pl011_set_baudrate()
147 struct pl011_data *data = dev->data; in pl011_is_readable()
149 if (!data->sbsa && in pl011_is_readable()
150 (!(get_uart(dev)->cr & PL011_CR_UARTEN) || !(get_uart(dev)->cr & PL011_CR_RXE))) { in pl011_is_readable()
154 return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U; in pl011_is_readable()
160 return -1; in pl011_poll_in()
164 *c = (unsigned char)get_uart(dev)->dr; in pl011_poll_in()
166 return get_uart(dev)->rsr & PL011_RSR_ERROR_MASK; in pl011_poll_in()
173 while (get_uart(dev)->fr & PL011_FR_TXFF) { in pl011_poll_out()
178 get_uart(dev)->dr = (uint32_t)c; in pl011_poll_out()
185 if (get_uart(dev)->rsr & PL011_RSR_ECR_OE) { in pl011_err_check()
189 if (get_uart(dev)->rsr & PL011_RSR_ECR_BE) { in pl011_err_check()
193 if (get_uart(dev)->rsr & PL011_RSR_ECR_PE) { in pl011_err_check()
197 if (get_uart(dev)->rsr & PL011_RSR_ECR_FE) { in pl011_err_check()
208 struct pl011_data *data = dev->data; in pl011_runtime_configure_internal()
210 int ret = -ENOTSUP; in pl011_runtime_configure_internal()
212 if (data->sbsa) { in pl011_runtime_configure_internal()
221 lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK | PL011_LCRH_STP2); in pl011_runtime_configure_internal()
223 switch (cfg->parity) { in pl011_runtime_configure_internal()
237 switch (cfg->stop_bits) { in pl011_runtime_configure_internal()
248 switch (cfg->data_bits) { in pl011_runtime_configure_internal()
265 switch (cfg->flow_ctrl) { in pl011_runtime_configure_internal()
277 ret = pl011_set_baudrate(dev, data->clk_freq, cfg->baudrate); in pl011_runtime_configure_internal()
283 get_uart(dev)->lcr_h = lcrh; in pl011_runtime_configure_internal()
285 memcpy(&data->uart_cfg, cfg, sizeof(data->uart_cfg)); in pl011_runtime_configure_internal()
308 struct pl011_data *data = dev->data; in pl011_runtime_config_get()
310 *cfg = data->uart_cfg; in pl011_runtime_config_get()
322 while (!(get_uart(dev)->fr & PL011_FR_TXFF) && (len - num_tx > 0)) { in pl011_fifo_fill()
323 get_uart(dev)->dr = tx_data[num_tx++]; in pl011_fifo_fill()
333 while ((len - num_rx > 0) && !(get_uart(dev)->fr & PL011_FR_RXFE)) { in pl011_fifo_read()
334 rx_data[num_rx++] = get_uart(dev)->dr; in pl011_fifo_read()
342 struct pl011_data *data = dev->data; in pl011_irq_tx_enable()
344 get_uart(dev)->imsc |= PL011_IMSC_TXIM; in pl011_irq_tx_enable()
345 if (data->sw_call_txdrdy) { in pl011_irq_tx_enable()
347 if (data->irq_cb) { in pl011_irq_tx_enable()
358 * functional-overview/interrupts in pl011_irq_tx_enable()
360 data->irq_cb(dev, data->irq_cb_data); in pl011_irq_tx_enable()
362 data->sw_call_txdrdy = false; in pl011_irq_tx_enable()
368 get_uart(dev)->imsc &= ~PL011_IMSC_TXIM; in pl011_irq_tx_disable()
374 return ((get_uart(dev)->fr & PL011_FR_BUSY) == 0); in pl011_irq_tx_complete()
379 struct pl011_data *data = dev->data; in pl011_irq_tx_ready()
381 if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_TXE)) { in pl011_irq_tx_ready()
385 return ((get_uart(dev)->imsc & PL011_IMSC_TXIM) && in pl011_irq_tx_ready()
387 (get_uart(dev)->ris & PL011_RIS_TXRIS || get_uart(dev)->fr & PL011_FR_TXFE)); in pl011_irq_tx_ready()
392 get_uart(dev)->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; in pl011_irq_rx_enable()
397 get_uart(dev)->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); in pl011_irq_rx_disable()
402 struct pl011_data *data = dev->data; in pl011_irq_rx_ready()
404 if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_RXE)) { in pl011_irq_rx_ready()
408 return ((get_uart(dev)->imsc & PL011_IMSC_RXIM) && in pl011_irq_rx_ready()
409 (!(get_uart(dev)->fr & PL011_FR_RXFE))); in pl011_irq_rx_ready()
415 get_uart(dev)->imsc |= PL011_IMSC_ERROR_MASK; in pl011_irq_err_enable()
420 get_uart(dev)->imsc &= ~PL011_IMSC_ERROR_MASK; in pl011_irq_err_disable()
437 struct pl011_data *data = dev->data; in pl011_irq_callback_set()
439 data->irq_cb = cb; in pl011_irq_callback_set()
440 data->irq_cb_data = cb_data; in pl011_irq_callback_set()
472 const struct pl011_config *config = dev->config; in pl011_init()
473 struct pl011_data *data = dev->data; in pl011_init()
479 if (config->reset.dev) { in pl011_init()
480 ret = reset_line_toggle_dt(&config->reset); in pl011_init()
488 if (config->clock_dev) { in pl011_init()
489 clock_control_on(config->clock_dev, config->clock_id); in pl011_init()
490 clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_freq); in pl011_init()
499 if (!data->sbsa) { in pl011_init()
501 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in pl011_init()
506 /* Call vendor-specific function to power on the peripheral */ in pl011_init()
507 if (config->pwr_on_func != NULL) { in pl011_init()
508 ret = config->pwr_on_func(); in pl011_init()
515 /* Call vendor-specific function to enable clock for the peripheral */ in pl011_init()
516 if (config->clk_enable_func != NULL) { in pl011_init()
517 ret = config->clk_enable_func(dev, data->clk_freq); in pl011_init()
523 pl011_runtime_configure_internal(dev, &data->uart_cfg, false); in pl011_init()
526 get_uart(dev)->ifls = FIELD_PREP(PL011_IFLS_TXIFLSEL_M, TXIFLSEL_1_8_FULL) in pl011_init()
533 get_uart(dev)->imsc = 0U; in pl011_init()
534 get_uart(dev)->icr = PL011_IMSC_MASK_ALL; in pl011_init()
536 if (!data->sbsa) { in pl011_init()
537 get_uart(dev)->dmacr = 0U; in pl011_init()
539 get_uart(dev)->cr &= ~PL011_CR_SIREN; in pl011_init()
540 get_uart(dev)->cr |= PL011_CR_RXE | PL011_CR_TXE; in pl011_init()
544 config->irq_config_func(dev); in pl011_init()
545 data->sw_call_txdrdy = true; in pl011_init()
547 if (!data->sbsa) { in pl011_init()
619 struct pl011_data *data = dev->data; in pl011_isr()
622 if (data->irq_cb) { in pl011_isr()
623 data->irq_cb(dev, data->irq_cb_data); in pl011_isr()