40 #include <hal/uhci_ll.h>
43 #include <hal/uart_ll.h>
44 #include <hal/uart_hal.h>
45 #include <hal/uart_types.h>
115 	uart_hal_context_t hal;  member
140 	if (uart_hal_get_rxfifo_len(&data->hal) == 0) {  in uart_esp32_poll_in()
144 	uart_hal_read_rxfifo(&data->hal, p_char, &inout_rd_len);  in uart_esp32_poll_in()
155 	while (uart_hal_get_txfifo_len(&data->hal) == 0) {  in uart_esp32_poll_out()
160 	uart_hal_write_txfifo(&data->hal, &c, 1, &written);  in uart_esp32_poll_out()
166 	uint32_t mask = uart_hal_get_intsts_mask(&data->hal);  in uart_esp32_err_check()
207 	uart_hal_get_sclk(&data->hal, &src_clk);  in uart_esp32_config_get()
211 	uart_hal_get_baudrate(&data->hal, &calc_baud, sclk_freq);  in uart_esp32_config_get()
214 	uart_hal_get_parity(&data->hal, &parity);  in uart_esp32_config_get()
229 	uart_hal_get_stop_bits(&data->hal, &stop_bit);  in uart_esp32_config_get()
244 	uart_hal_get_data_bit_num(&data->hal, &data_bit);  in uart_esp32_config_get()
262 	uart_hal_get_hw_flow_ctrl(&data->hal, &hw_flow);  in uart_esp32_config_get()
274 	if (uart_hal_is_mode_rs485_half_duplex(&data->hal)) {  in uart_esp32_config_get()
301 	uart_hal_set_sclk(&data->hal, UART_SCLK_DEFAULT);  in uart_esp32_configure()
302 	uart_hal_set_rxfifo_full_thr(&data->hal, UART_RX_FIFO_THRESH);  in uart_esp32_configure()
303 	uart_hal_set_txfifo_empty_thr(&data->hal, UART_TX_FIFO_THRESH);  in uart_esp32_configure()
304 	uart_hal_rxfifo_rst(&data->hal);  in uart_esp32_configure()
305 	uart_hal_txfifo_rst(&data->hal);  in uart_esp32_configure()
309 		uart_hal_set_parity(&data->hal, UART_PARITY_DISABLE);  in uart_esp32_configure()
312 		uart_hal_set_parity(&data->hal, UART_PARITY_EVEN);  in uart_esp32_configure()
315 		uart_hal_set_parity(&data->hal, UART_PARITY_ODD);  in uart_esp32_configure()
323 		uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1);  in uart_esp32_configure()
326 		uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1_5);  in uart_esp32_configure()
329 		uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_2);  in uart_esp32_configure()
337 		uart_hal_set_data_bit_num(&data->hal, UART_DATA_5_BITS);  in uart_esp32_configure()
340 		uart_hal_set_data_bit_num(&data->hal, UART_DATA_6_BITS);  in uart_esp32_configure()
343 		uart_hal_set_data_bit_num(&data->hal, UART_DATA_7_BITS);  in uart_esp32_configure()
346 		uart_hal_set_data_bit_num(&data->hal, UART_DATA_8_BITS);  in uart_esp32_configure()
352 	uart_hal_set_mode(&data->hal, UART_MODE_UART);  in uart_esp32_configure()
356 		uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_DISABLE, 0);  in uart_esp32_configure()
359 		uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_CTS_RTS, 10);  in uart_esp32_configure()
362 		uart_hal_set_mode(&data->hal, UART_MODE_RS485_HALF_DUPLEX);  in uart_esp32_configure()
368 	uart_hal_get_sclk(&data->hal, &src_clk);  in uart_esp32_configure()
371 	uart_hal_set_baudrate(&data->hal, cfg->baudrate, sclk_freq);  in uart_esp32_configure()
373 	uart_hal_set_rx_timeout(&data->hal, 0x16);  in uart_esp32_configure()
376 		uart_hal_inverse_signal(&data->hal, UART_SIGNAL_TXD_INV);  in uart_esp32_configure()
380 		uart_hal_inverse_signal(&data->hal, UART_SIGNAL_RXD_INV);  in uart_esp32_configure()
396 	uart_hal_write_txfifo(&data->hal, tx_data, len, &written);  in uart_esp32_fifo_fill()
403 	const int num_rx = uart_hal_get_rxfifo_len(&data->hal);  in uart_esp32_fifo_read()
410 	uart_hal_read_rxfifo(&data->hal, rx_data, &read);  in uart_esp32_fifo_read()
418 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);  in uart_esp32_irq_tx_enable()
419 	uart_hal_ena_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);  in uart_esp32_irq_tx_enable()
426 	uart_hal_disable_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);  in uart_esp32_irq_tx_disable()
433 	return (uart_hal_get_txfifo_len(&data->hal) > 0 &&  in uart_esp32_irq_tx_ready()
434 		uart_hal_get_intr_ena_status(&data->hal) & UART_INTR_TXFIFO_EMPTY);  in uart_esp32_irq_tx_ready()
441 	uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);  in uart_esp32_irq_rx_disable()
442 	uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);  in uart_esp32_irq_rx_disable()
449 	return uart_hal_is_tx_idle(&data->hal);  in uart_esp32_irq_tx_complete()
456 	return (uart_hal_get_rxfifo_len(&data->hal) > 0);  in uart_esp32_irq_rx_ready()
464 	uart_hal_ena_intr_mask(&data->hal, UART_INTR_FRAM_ERR);  in uart_esp32_irq_err_enable()
465 	uart_hal_ena_intr_mask(&data->hal, UART_INTR_PARITY_ERR);  in uart_esp32_irq_err_enable()
472 	uart_hal_disable_intr_mask(&data->hal, UART_INTR_FRAM_ERR);  in uart_esp32_irq_err_disable()
473 	uart_hal_disable_intr_mask(&data->hal, UART_INTR_PARITY_ERR);  in uart_esp32_irq_err_disable()
485 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);  in uart_esp32_irq_update()
486 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);  in uart_esp32_irq_update()
487 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);  in uart_esp32_irq_update()
525 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);  in uart_esp32_irq_rx_enable()
526 	uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);  in uart_esp32_irq_rx_enable()
527 	uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);  in uart_esp32_irq_rx_enable()
528 	uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);  in uart_esp32_irq_rx_enable()
535 	uint32_t uart_intr_status = uart_hal_get_intsts_mask(&data->hal);  in uart_esp32_isr()
540 	uart_hal_clr_intsts_mask(&data->hal, uart_intr_status);  in uart_esp32_isr()
845 	uart_hal_set_rxfifo_full_thr(&data->hal, 1);  in uart_esp32_async_rx_enable()
983 		uhci_ll_attach_uart_port(data->uhci_dev, uart_hal_get_port_num(&data->hal));  in uart_esp32_init()
1069 		.hal =                                                                             \