Lines Matching +full:0 +full:x08

26 #define BMP5_SET_LOW_BYTE  0x00FFu
27 #define BMP5_SET_HIGH_BYTE 0xFF00u
45 #define BMP5_OK      0
47 #define BMP5_DISABLE 0u
50 #define BMP5_REG_CHIP_ID         0x01
51 #define BMP5_REG_REV_ID          0x02
52 #define BMP5_REG_CHIP_STATUS     0x11
53 #define BMP5_REG_DRIVE_CONFIG    0x13
54 #define BMP5_REG_INT_CONFIG      0x14
55 #define BMP5_REG_INT_SOURCE      0x15
56 #define BMP5_REG_FIFO_CONFIG     0x16
57 #define BMP5_REG_FIFO_COUNT      0x17
58 #define BMP5_REG_FIFO_SEL        0x18
59 #define BMP5_REG_TEMP_DATA_XLSB  0x1D
60 #define BMP5_REG_TEMP_DATA_LSB   0x1E
61 #define BMP5_REG_TEMP_DATA_MSB   0x1F
62 #define BMP5_REG_PRESS_DATA_XLSB 0x20
63 #define BMP5_REG_PRESS_DATA_LSB  0x21
64 #define BMP5_REG_PRESS_DATA_MSB  0x22
65 #define BMP5_REG_INT_STATUS      0x27
66 #define BMP5_REG_STATUS          0x28
67 #define BMP5_REG_FIFO_DATA       0x29
68 #define BMP5_REG_NVM_ADDR        0x2B
69 #define BMP5_REG_NVM_DATA_LSB    0x2C
70 #define BMP5_REG_NVM_DATA_MSB    0x2D
71 #define BMP5_REG_DSP_CONFIG      0x30
72 #define BMP5_REG_DSP_IIR         0x31
73 #define BMP5_REG_OOR_THR_P_LSB   0x32
74 #define BMP5_REG_OOR_THR_P_MSB   0x33
75 #define BMP5_REG_OOR_RANGE       0x34
76 #define BMP5_REG_OOR_CONFIG      0x35
77 #define BMP5_REG_OSR_CONFIG      0x36
78 #define BMP5_REG_ODR_CONFIG      0x37
79 #define BMP5_REG_OSR_EFF         0x38
80 #define BMP5_REG_CMD             0x7E
84 #define BMP5_CHIP_ID_PRIM 0x50
85 #define BMP5_CHIP_ID_SEC  0x51
88 #define BMP5_I2C_ADDR_PRIM 0x46
89 #define BMP5_I2C_ADDR_SEC  0x47
92 #define BMP5_NVM_START_ADDR 0x20
93 #define BMP5_NVM_END_ADDR   0x22
96 #define BMP5_SPI_RD_MASK 0x80
105 #define BMP5_SOFT_RESET_CMD 0xB6
108 #define BMP5_NVM_FIRST_CMND        0x5D
109 #define BMP5_NVM_READ_ENABLE_CMND  0xA5
110 #define BMP5_NVM_WRITE_ENABLE_CMND 0xA0
113 #define BMP5_DEEP_ENABLED  0
117 #define BMP5_FIFO_EMPTY                  0X7F
118 #define BMP5_FIFO_MAX_THRESHOLD_P_T_MODE 0x0F
119 #define BMP5_FIFO_MAX_THRESHOLD_P_MODE   0x1F
122 #define BMP5_IIR_BYPASS 0xC0
125 #define BMP5_OOR_COUNT_LIMIT_1  0x00
126 #define BMP5_OOR_COUNT_LIMIT_3  0x01
127 #define BMP5_OOR_COUNT_LIMIT_7  0x02
128 #define BMP5_OOR_COUNT_LIMIT_15 0x03
131 #define BMP5_INT_MODE_PULSED  0
134 #define BMP5_INT_POL_ACTIVE_LOW  0
137 #define BMP5_INT_OD_PUSHPULL  0
141 #define BMP5_INT_ASSERTED_DRDY                   0x01
142 #define BMP5_INT_ASSERTED_FIFO_FULL              0x02
143 #define BMP5_INT_ASSERTED_FIFO_THRES             0x04
144 #define BMP5_INT_ASSERTED_PRESSURE_OOR           0x08
145 #define BMP5_INT_ASSERTED_POR_SOFTRESET_COMPLETE 0x10
146 #define BMP5_INT_NVM_RDY                         0x02
147 #define BMP5_INT_NVM_ERR                         0x04
148 #define BMP5_INT_NVM_CMD_ERR                     0x08
151 #define BMP5_INT_MODE_MSK 0x01
153 #define BMP5_INT_POL_MSK 0x02
156 #define BMP5_INT_OD_MSK 0x04
159 #define BMP5_INT_EN_MSK 0x08
162 #define BMP5_INT_DRDY_EN_MSK 0x01
164 #define BMP5_INT_FIFO_FULL_EN_MSK 0x02
167 #define BMP5_INT_FIFO_THRES_EN_MSK 0x04
170 #define BMP5_INT_OOR_PRESS_EN_MSK 0x08
174 #define BMP5_ODR_MSK 0x7C
178 #define BMP5_TEMP_OS_MSK 0x07
180 #define BMP5_PRESS_OS_MSK 0x38
184 #define BMP5_PRESS_EN_MSK 0x40
188 #define BMP5_SET_IIR_TEMP_MSK 0x07
190 #define BMP5_SET_IIR_PRESS_MSK 0x38
193 #define BMP5_OOR_SEL_IIR_PRESS_MSK 0x80
196 #define BMP5_SHDW_SET_IIR_TEMP_MSK 0x08
199 #define BMP5_SHDW_SET_IIR_PRESS_MSK 0x20
202 #define BMP5_SET_FIFO_IIR_TEMP_MSK 0x10
205 #define BMP5_SET_FIFO_IIR_PRESS_MSK 0x40
208 #define BMP5_IIR_FLUSH_FORCED_EN_MSK 0x04
212 #define BMP5_OSR_TEMP_EFF_MSK 0x07
214 #define BMP5_OSR_PRESS_EFF_MSK 0x38
217 #define BMP5_ODR_IS_VALID_MSK 0x80
221 #define BMP5_POWERMODE_MSK 0x03
223 #define BMP5_DEEP_DISABLE_MSK 0x80
227 #define BMP5_FIFO_THRESHOLD_MSK 0x1F
229 #define BMP5_FIFO_MODE_MSK 0x20
232 #define BMP5_FIFO_DEC_SEL_MSK 0x1C
235 #define BMP5_FIFO_COUNT_MSK 0x3F
237 #define BMP5_FIFO_FRAME_SEL_MSK 0x03
240 #define BMP5_OOR_THR_P_LSB_MSK 0x0000FF
242 #define BMP5_OOR_THR_P_MSB_MSK 0x00FF00
244 #define BMP5_OOR_THR_P_XMSB_MSK 0x010000
247 /* Macro to mask xmsb value of oor threshold from register(0x35) value */
248 #define BMP5_OOR_THR_P_XMSB_REG_MSK 0x01
250 #define BMP5_OOR_COUNT_LIMIT_MSK 0xC0
254 #define BMP5_NVM_ADDR_MSK 0x3F
256 #define BMP5_NVM_PROG_EN_MSK 0x40
259 #define BMP5_NVM_DATA_LSB_MSK 0x00FF
261 #define BMP5_NVM_DATA_MSB_MSK 0xFF00