Lines Matching +full:rx +full:- +full:sync +full:- +full:mode
4 * SPDX-License-Identifier: Apache-2.0
109 struct mmc_rcar_data *data = dev->data; in rcar_mmc_reset_and_mask_irqs()
124 k_sem_reset(&data->irq_xref_fin); in rcar_mmc_reset_and_mask_irqs()
138 * @retval -EINVAL: the dev pointer is NULL
145 return -EINVAL; in rcar_mmc_card_busy()
160 * @retval -ETIMEDOUT: timed out while tx/rx
161 * @retval -EIO: I/O error
162 * @retval -EILSEQ: communication out of sync
170 return -ETIMEDOUT; in rcar_mmc_check_errors()
174 LOG_DBG("communication out of sync 0x%08x", info2); in rcar_mmc_check_errors()
175 return -EILSEQ; in rcar_mmc_check_errors()
180 return -EIO; in rcar_mmc_check_errors()
200 * @retval -ETIMEDOUT: timed out while tx/rx
201 * @retval -EIO: I/O error
202 * @retval -EILSEQ: communication out of sync
214 return -ETIMEDOUT; in rcar_mmc_poll_reg_flags_check_err()
225 LOG_DBG("%s: an error occurs on the DMAC channel #%u", dev->name, in rcar_mmc_poll_reg_flags_check_err()
227 return -EIO; in rcar_mmc_poll_reg_flags_check_err()
231 timeout_us -= MMC_POLL_FLAGS_ONE_CYCLE_TIMEOUT_US; in rcar_mmc_poll_reg_flags_check_err()
259 * @retval -ETIMEDOUT: controller reset timed out
260 * @retval -EINVAL: the dev pointer is NULL
261 * @retval -EILSEQ: communication out of sync
262 * @retval -ENOTSUP: controller does not support I/O
276 * * WIDTH (15) and WIDTH8 (13) set to 0, which equal to 4-bits bus;
277 * * Timeout Mode Select (EXTOP - 9) is set to 0;
278 * * Timeout Mask (TOUTMASK - 8) is set to 0;
279 * * Timeout Counter (TOP27-TOP24 bits 7-4) is equal to 0b1110;
280 * * Card Detect Time Counter (CTOP24-CTOP21 bits 3-0) is equal to 0b1110;
282 * * E13 default state 1 (E12-E14 it is CRC status 0b010);
295 return -EINVAL; in rcar_mmc_reset()
298 data = dev->data; in rcar_mmc_reset()
319 can_retune = data->can_retune; in rcar_mmc_reset()
325 if (data->restore_cfg_after_reset) { in rcar_mmc_reset()
328 memcpy(&ios, &data->host_io, sizeof(ios)); in rcar_mmc_reset()
329 memset(&data->host_io, 0, sizeof(ios)); in rcar_mmc_reset()
331 data->host_io.power_mode = ios.power_mode; in rcar_mmc_reset()
349 data->ddr_mode = 0; in rcar_mmc_reset()
350 data->host_io.bus_width = SDHC_BUS_WIDTH4BIT; in rcar_mmc_reset()
351 data->host_io.timing = SDHC_TIMING_LEGACY; in rcar_mmc_reset()
352 data->is_last_cmd_app_cmd = 0; in rcar_mmc_reset()
368 * @retval -ETIMEDOUT: card busy flag is set during long time
390 return -ETIMEDOUT; in rcar_mmc_enable_clock()
440 return -EINVAL; in rcar_mmc_convert_sd_to_mmc_resp()
470 cmd->response[0] = (rsp_39_8 & 0xffffff) << 8; in rcar_mmc_extract_resp()
471 cmd->response[1] = in rcar_mmc_extract_resp()
473 cmd->response[2] = in rcar_mmc_extract_resp()
475 cmd->response[3] = in rcar_mmc_extract_resp()
480 cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3]); in rcar_mmc_extract_resp()
482 cmd->response[0] = rcar_mmc_read_reg32(dev, RCAR_MMC_RSP10); in rcar_mmc_extract_resp()
483 LOG_DBG("Response %u\n\t[0]: 0x%08x", response_type, cmd->response[0]); in rcar_mmc_extract_resp()
487 /* configure CMD register for tx/rx data */
492 switch (cmd->opcode) { in rcar_mmc_gen_data_cmd()
515 if (data->blocks > 1) { in rcar_mmc_gen_data_cmd()
530 * @param data MMC data buffer for tx/rx
533 * @retval 0 tx/rx was successful
534 * @retval -ENOTSUP: cache flush/invalidate aren't supported
535 * @retval -ETIMEDOUT: timed out while tx/rx
536 * @retval -EIO: I/O error
537 * @retval -EILSEQ: communication out of sync
546 struct mmc_rcar_data *dev_data = dev->data; in rcar_mmc_dma_rx_tx_data()
549 ret = sys_cache_data_flush_range(data->data, data->blocks * data->block_size); in rcar_mmc_dma_rx_tx_data()
551 LOG_ERR("%s: can't invalidate data cache before write", dev->name); in rcar_mmc_dma_rx_tx_data()
569 dma_addr = k_mem_phys_addr(data->data); in rcar_mmc_dma_rx_tx_data()
584 ret = k_sem_take(&dev_data->irq_xref_fin, K_MSEC(data->timeout_ms)); in rcar_mmc_dma_rx_tx_data()
586 LOG_ERR("%s: interrupt signal timeout error %d", dev->name, ret); in rcar_mmc_dma_rx_tx_data()
591 LOG_ERR("%s: an error occurs on the DMAC channel #%u", dev->name, in rcar_mmc_dma_rx_tx_data()
593 ret = -EIO; in rcar_mmc_dma_rx_tx_data()
599 data->timeout_ms * 1000LL); in rcar_mmc_dma_rx_tx_data()
603 if (sys_cache_data_invd_range(data->data, data->blocks * data->block_size) < 0) { in rcar_mmc_dma_rx_tx_data()
604 LOG_ERR("%s: can't invalidate data cache after read", dev->name); in rcar_mmc_dma_rx_tx_data()
612 if (ret == -EIO) { in rcar_mmc_dma_rx_tx_data()
627 struct mmc_rcar_data *dev_data = dev->data; in rcar_mmc_read_buf0()
628 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0; in rcar_mmc_read_buf0()
652 struct mmc_rcar_data *dev_data = dev->data; in rcar_mmc_write_buf0()
653 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0; in rcar_mmc_write_buf0()
680 * @param data MMC data buffer for tx/rx
683 * @retval 0 tx/rx was successful
684 * @retval -EINVAL: invalid block size
685 * @retval -ETIMEDOUT: timed out while tx/rx
686 * @retval -EIO: I/O error
687 * @retval -EILSEQ: communication out of sync
692 struct mmc_rcar_data *dev_data = dev->data; in rcar_mmc_sd_buf_rx_tx_data()
696 uint8_t sd_buf0_size = dev_data->width_access_sd_buf0; in rcar_mmc_sd_buf_rx_tx_data()
697 uint16_t aligned_block_size = ROUND_UP(data->block_size, sd_buf0_size); in rcar_mmc_sd_buf_rx_tx_data()
699 int64_t remaining_timeout_us = data->timeout_ms * 1000LL; in rcar_mmc_sd_buf_rx_tx_data()
706 if ((data->block_size % dev_data->width_access_sd_buf0) || in rcar_mmc_sd_buf_rx_tx_data()
707 (data->block_size < dev_data->width_access_sd_buf0)) { in rcar_mmc_sd_buf_rx_tx_data()
709 dev->name, data->block_size, dev_data->width_access_sd_buf0); in rcar_mmc_sd_buf_rx_tx_data()
710 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
714 * JEDEC Standard No. 84-B51 in rcar_mmc_sd_buf_rx_tx_data()
715 * 6.6.24 Dual Data Rate mode operation: in rcar_mmc_sd_buf_rx_tx_data()
720 * 4.12.6 Timing Changes in DDR50 Mode in rcar_mmc_sd_buf_rx_tx_data()
724 if (dev_data->ddr_mode && data->block_size != 512) { in rcar_mmc_sd_buf_rx_tx_data()
725 LOG_ERR("%s: block size (%u) isn't equal to 512 in DDR mode", dev->name, in rcar_mmc_sd_buf_rx_tx_data()
726 data->block_size); in rcar_mmc_sd_buf_rx_tx_data()
727 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
732 * transfer data length register from R-Car S4 series User's Manual in rcar_mmc_sd_buf_rx_tx_data()
734 if (data->block_size > 512 || data->block_size == 0) { in rcar_mmc_sd_buf_rx_tx_data()
736 dev->name, data->block_size); in rcar_mmc_sd_buf_rx_tx_data()
737 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
743 if (!(cmd_reg & RCAR_MMC_CMD_NOSTOP) && data->block_size != 512) { in rcar_mmc_sd_buf_rx_tx_data()
744 LOG_ERR("%s: illegal block size (%u) for multi-block xref with CMD12", in rcar_mmc_sd_buf_rx_tx_data()
745 dev->name, data->block_size); in rcar_mmc_sd_buf_rx_tx_data()
746 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
749 switch (data->block_size) { in rcar_mmc_sd_buf_rx_tx_data()
757 LOG_ERR("%s: illegal block size (%u) for multi-block xref without CMD12", in rcar_mmc_sd_buf_rx_tx_data()
758 dev->name, data->block_size); in rcar_mmc_sd_buf_rx_tx_data()
759 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
763 if (data->block_size == 1 && dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) { in rcar_mmc_sd_buf_rx_tx_data()
764 LOG_ERR("%s: block size can't be equal to 1 with 8-bits bus width", dev->name); in rcar_mmc_sd_buf_rx_tx_data()
765 return -EINVAL; in rcar_mmc_sd_buf_rx_tx_data()
768 for (block = 0; block < data->blocks; block++) { in rcar_mmc_sd_buf_rx_tx_data()
769 uint8_t *buf = (uint8_t *)data->data + (block * data->block_size); in rcar_mmc_sd_buf_rx_tx_data()
789 uint8_t copy_size = MIN(sd_buf0_size, data->block_size - w_off); in rcar_mmc_sd_buf_rx_tx_data()
800 remaining_timeout_us -= in rcar_mmc_sd_buf_rx_tx_data()
801 k_ticks_to_us_ceil64(k_uptime_ticks()) - start_block_xref_us; in rcar_mmc_sd_buf_rx_tx_data()
803 return -ETIMEDOUT; in rcar_mmc_sd_buf_rx_tx_data()
818 * @param data MMC data buffer for tx/rx
821 * @retval 0 tx/rx was successful
822 * @retval -EINVAL: invalid block size
823 * @retval -ETIMEDOUT: timed out while tx/rx
824 * @retval -EIO: I/O error
825 * @retval -EILSEQ: communication out of sync
833 if (!(k_mem_phys_addr(data->data) >> 32)) { in rcar_mmc_rx_tx_data()
870 * @retval -ETIMEDOUT: command timed out while sending
871 * @retval -ENOTSUP: host controller does not support command
872 * @retval -EIO: I/O error
873 * @retval -EILSEQ: communication out of sync
878 int ret = -ENOTSUP; in rcar_mmc_request()
886 return -EINVAL; in rcar_mmc_request()
889 dev_data = dev->data; in rcar_mmc_request()
890 response_type = cmd->response_type & SDHC_NATIVE_RESPONSE_MASK; in rcar_mmc_request()
891 attempts = cmd->retries + 1; in rcar_mmc_request()
893 while (ret && attempts-- > 0) { in rcar_mmc_request()
894 if (ret != -ENOTSUP) { in rcar_mmc_request()
904 ret = -EBUSY; in rcar_mmc_request()
910 rcar_mmc_write_reg32(dev, RCAR_MMC_ARG, cmd->arg); in rcar_mmc_request()
912 reg = cmd->opcode; in rcar_mmc_request()
915 rcar_mmc_write_reg32(dev, RCAR_MMC_SIZE, data->block_size); in rcar_mmc_request()
916 rcar_mmc_write_reg32(dev, RCAR_MMC_SECCNT, data->blocks); in rcar_mmc_request()
922 if (dev_data->is_last_cmd_app_cmd) { in rcar_mmc_request()
929 return -EINVAL; in rcar_mmc_request()
934 LOG_DBG("(SD_CMD=%08x, SD_ARG=%08x)", cmd->opcode, cmd->arg); in rcar_mmc_request()
940 cmd->timeout_ms * 1000LL); in rcar_mmc_request()
972 dev_data->is_last_cmd_app_cmd = (cmd->opcode == SD_APP_CMD); in rcar_mmc_request()
1023 if (!ios->signal_voltage || ios->signal_voltage == host_io->signal_voltage) { in rcar_mmc_change_voltage()
1027 switch (ios->signal_voltage) { in rcar_mmc_change_voltage()
1029 ret = regulator_set_voltage(cfg->regulator_vqmmc, 3300000, 3300000); in rcar_mmc_change_voltage()
1030 if (ret && ret != -ENOSYS) { in rcar_mmc_change_voltage()
1034 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in rcar_mmc_change_voltage()
1037 ret = regulator_set_voltage(cfg->regulator_vqmmc, 1800000, 1800000); in rcar_mmc_change_voltage()
1038 if (ret && ret != -ENOSYS) { in rcar_mmc_change_voltage()
1042 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_UHS); in rcar_mmc_change_voltage()
1048 ret = -ENOTSUP; in rcar_mmc_change_voltage()
1053 host_io->signal_voltage = ios->signal_voltage; in rcar_mmc_change_voltage()
1064 val--; in round_up_next_pwr_of_2()
1077 * @note In the case of data transfer in HS400 mode (HS400 bit in
1079 * @note In the case of writing of one-byte block, 8-bit width cannot
1081 * or 1 bit before writing one-byte block.
1087 * @retval -ENOTSUP: controller does not support these I/O settings
1088 * @retval -ETIMEDOUT: card busy flag is set during long time
1095 struct mmc_rcar_data *data = dev->data; in rcar_mmc_set_clk_rate()
1096 const struct mmc_rcar_cfg *cfg = dev->config; in rcar_mmc_set_clk_rate()
1097 struct sdhc_io *host_io = &data->host_io; in rcar_mmc_set_clk_rate()
1099 if (host_io->clock == ios->clock) { in rcar_mmc_set_clk_rate()
1103 if (ios->clock == 0) { in rcar_mmc_set_clk_rate()
1104 host_io->clock = 0; in rcar_mmc_set_clk_rate()
1108 if (ios->clock > data->props.f_max || ios->clock < data->props.f_min) { in rcar_mmc_set_clk_rate()
1109 LOG_ERR("SDHC I/O: clock (%d) isn't in range %d - %d Hz", ios->clock, in rcar_mmc_set_clk_rate()
1110 data->props.f_min, data->props.f_max); in rcar_mmc_set_clk_rate()
1111 return -EINVAL; in rcar_mmc_set_clk_rate()
1114 divisor = DIV_ROUND_UP(cfg->max_frequency, ios->clock); in rcar_mmc_set_clk_rate()
1116 /* Do not set divider to 0xff in DDR mode */ in rcar_mmc_set_clk_rate()
1117 if (data->ddr_mode && (divisor == 1)) { in rcar_mmc_set_clk_rate()
1140 host_io->clock = ios->clock; in rcar_mmc_set_clk_rate()
1151 return -ETIMEDOUT; in rcar_mmc_set_clk_rate()
1163 host_io->clock = ios->clock; in rcar_mmc_set_clk_rate()
1165 LOG_DBG("%s: set clock rate to %d", dev->name, ios->clock); in rcar_mmc_set_clk_rate()
1174 * @note In the case of data transfer in HS400 mode (HS400 bit in
1176 * @note In the case of writing of one-byte block, 8-bit width cannot
1178 * or 1 bit before writing one-byte block.
1184 * @retval -ENOTSUP: controller does not support these I/O settings
1185 * @retval -ETIMEDOUT: card busy flag is set during long time
1192 struct mmc_rcar_data *data = dev->data; in rcar_mmc_set_bus_width()
1193 struct sdhc_io *host_io = &data->host_io; in rcar_mmc_set_bus_width()
1196 if (host_io->bus_width == ios->bus_width) { in rcar_mmc_set_bus_width()
1200 if (!ios->bus_width) { in rcar_mmc_set_bus_width()
1204 switch (ios->bus_width) { in rcar_mmc_set_bus_width()
1209 if (data->props.host_caps.bus_4_bit_support) { in rcar_mmc_set_bus_width()
1212 LOG_ERR("SDHC I/O: 4-bits bus width isn't supported"); in rcar_mmc_set_bus_width()
1213 return -ENOTSUP; in rcar_mmc_set_bus_width()
1217 if (data->props.host_caps.bus_8_bit_support) { in rcar_mmc_set_bus_width()
1220 LOG_ERR("SDHC I/O: 8-bits bus width isn't supported"); in rcar_mmc_set_bus_width()
1221 return -ENOTSUP; in rcar_mmc_set_bus_width()
1225 return -ENOTSUP; in rcar_mmc_set_bus_width()
1235 return -ETIMEDOUT; in rcar_mmc_set_bus_width()
1243 host_io->bus_width = ios->bus_width; in rcar_mmc_set_bus_width()
1245 LOG_DBG("%s: set bus-width to %d", dev->name, host_io->bus_width); in rcar_mmc_set_bus_width()
1250 * set DDR mode on MMC controller according to value inside
1257 struct mmc_rcar_data *data = dev->data; in rcar_mmc_set_ddr_mode()
1266 return -ETIMEDOUT; in rcar_mmc_set_ddr_mode()
1270 if (data->ddr_mode) { in rcar_mmc_set_ddr_mode()
1271 /* HS400 mode (DDR mode) */ in rcar_mmc_set_ddr_mode()
1274 /* Normal mode (default, high speed, or SDR) */ in rcar_mmc_set_ddr_mode()
1285 * For now function only can enable DDR mode and call the function for
1294 * @retval -ENOTSUP: controller does not support these I/O settings
1295 * @retval -ETIMEDOUT: card busy flag is set during long time
1300 struct mmc_rcar_data *data = dev->data; in rcar_mmc_set_timings()
1301 struct sdhc_io *host_io = &data->host_io; in rcar_mmc_set_timings()
1302 enum sd_voltage new_voltage = host_io->signal_voltage; in rcar_mmc_set_timings()
1304 if (host_io->timing == ios->timing) { in rcar_mmc_set_timings()
1308 if (!host_io->timing) { in rcar_mmc_set_timings()
1312 data->ddr_mode = 0; in rcar_mmc_set_timings()
1314 switch (ios->timing) { in rcar_mmc_set_timings()
1318 if (!data->props.host_caps.high_spd_support) { in rcar_mmc_set_timings()
1320 return -ENOTSUP; in rcar_mmc_set_timings()
1328 if (!data->props.host_caps.sdr104_support) { in rcar_mmc_set_timings()
1330 return -ENOTSUP; in rcar_mmc_set_timings()
1334 if (!data->props.host_caps.hs400_support) { in rcar_mmc_set_timings()
1336 return -ENOTSUP; in rcar_mmc_set_timings()
1339 data->ddr_mode = 1; in rcar_mmc_set_timings()
1343 if (!data->props.host_caps.ddr50_support) { in rcar_mmc_set_timings()
1345 return -ENOTSUP; in rcar_mmc_set_timings()
1347 data->ddr_mode = 1; in rcar_mmc_set_timings()
1350 if (!data->props.host_caps.hs200_support) { in rcar_mmc_set_timings()
1352 return -ENOTSUP; in rcar_mmc_set_timings()
1357 return -ENOTSUP; in rcar_mmc_set_timings()
1360 ios->signal_voltage = new_voltage; in rcar_mmc_set_timings()
1361 if (rcar_mmc_change_voltage(dev->config, host_io, ios)) { in rcar_mmc_set_timings()
1362 return -ENOTSUP; in rcar_mmc_set_timings()
1370 host_io->timing = ios->timing; in rcar_mmc_set_timings()
1385 * @retval -ENOTSUP: controller does not support these I/O settings
1386 * @retval -EINVAL: some of pointers provided to the function are NULL
1387 * @retval -ETIMEDOUT: card busy flag is set during long time
1395 if (!dev || !ios || !dev->data || !dev->config) { in rcar_mmc_set_io()
1396 return -EINVAL; in rcar_mmc_set_io()
1399 data = dev->data; in rcar_mmc_set_io()
1400 host_io = &data->host_io; in rcar_mmc_set_io()
1404 ios->bus_width, ios->clock, ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF", in rcar_mmc_set_io()
1405 rcar_mmc_get_timing_str(ios->timing), in rcar_mmc_set_io()
1406 rcar_mmc_get_signal_voltage_str(ios->signal_voltage)); in rcar_mmc_set_io()
1412 host_io->clock, ios->clock); in rcar_mmc_set_io()
1417 * Set card bus mode in rcar_mmc_set_io()
1420 * 4.7.1 Command Types: "... there is no Open Drain mode in SD Memory Card" in rcar_mmc_set_io()
1422 * The use of open-drain mode is not possible in SD memory cards because the SD bus uses in rcar_mmc_set_io()
1423 * push-pull signaling, where both the host and the card can actively drive the data lines in rcar_mmc_set_io()
1426 * signal line needs to be actively driven high or low. The use of open-drain mode in this in rcar_mmc_set_io()
1430 * JEDEC Standard No. 84-B51, 10 The eMMC bus: in rcar_mmc_set_io()
1432 * - CMD: Command is a bidirectional signal. The host and Device drivers are operating in in rcar_mmc_set_io()
1434 * - DAT0-7: Data lines are bidirectional signals. Host and Device drivers are operating in rcar_mmc_set_io()
1435 * in push-pull mode. in rcar_mmc_set_io()
1436 * - CLK: Clock is a host to Device signal. CLK operates in push-pull mode. in rcar_mmc_set_io()
1437 * - Data Strobe: Data Strobe is a Device to host signal. Data Strobe operates in in rcar_mmc_set_io()
1438 * push-pull mode." in rcar_mmc_set_io()
1440 * So, open-drain mode signaling is supported in eMMC as one of the signaling modes for in rcar_mmc_set_io()
1443 * handles low-level operations such as protocol handling, data transfer, and error in rcar_mmc_set_io()
1444 * checking and should take care of the low-level details of communicating with the in rcar_mmc_set_io()
1445 * MMC/SD card, including setting the bus mode. Moreover, we can use only MMIO mode, the in rcar_mmc_set_io()
1448 * protocols like SPI or SDIO. Finally, R-Car Gen3 and Gen4 "User’s manuals: Hardware" in rcar_mmc_set_io()
1449 * don't have direct configurations for open-drain mode for both PFC and GPIO and Zephyr in rcar_mmc_set_io()
1450 * SDHC subsystem doesn't support any bus mode except push-pull. in rcar_mmc_set_io()
1452 if (ios->bus_mode != SDHC_BUSMODE_PUSHPULL) { in rcar_mmc_set_io()
1453 LOG_ERR("SDHC I/O: not supported bus mode %d", ios->bus_mode); in rcar_mmc_set_io()
1454 return -ENOTSUP; in rcar_mmc_set_io()
1456 host_io->bus_mode = ios->bus_mode; in rcar_mmc_set_io()
1459 if (ios->power_mode && host_io->power_mode != ios->power_mode) { in rcar_mmc_set_io()
1460 const struct mmc_rcar_cfg *cfg = dev->config; in rcar_mmc_set_io()
1462 switch (ios->power_mode) { in rcar_mmc_set_io()
1464 ret = regulator_enable(cfg->regulator_vmmc); in rcar_mmc_set_io()
1469 k_msleep(data->props.power_delay); in rcar_mmc_set_io()
1471 ret = regulator_enable(cfg->regulator_vqmmc); in rcar_mmc_set_io()
1476 k_msleep(data->props.power_delay); in rcar_mmc_set_io()
1480 if (regulator_is_enabled(cfg->regulator_vqmmc)) { in rcar_mmc_set_io()
1481 ret = regulator_disable(cfg->regulator_vqmmc); in rcar_mmc_set_io()
1487 if (regulator_is_enabled(cfg->regulator_vmmc)) { in rcar_mmc_set_io()
1488 ret = regulator_disable(cfg->regulator_vmmc); in rcar_mmc_set_io()
1497 LOG_ERR("SDHC I/O: not supported power mode %d", ios->power_mode); in rcar_mmc_set_io()
1498 return -ENOTSUP; in rcar_mmc_set_io()
1504 host_io->power_mode = ios->power_mode; in rcar_mmc_set_io()
1510 host_io->bus_width, ios->bus_width); in rcar_mmc_set_io()
1517 host_io->timing, ios->timing); in rcar_mmc_set_io()
1521 ret = rcar_mmc_change_voltage(dev->config, host_io, ios); in rcar_mmc_set_io()
1524 host_io->signal_voltage, ios->signal_voltage); in rcar_mmc_set_io()
1540 * @retval -EINVAL: some of pointers provided to the function are NULL
1546 if (!dev || !dev->config) { in rcar_mmc_get_card_present()
1547 return -EINVAL; in rcar_mmc_get_card_present()
1550 cfg = dev->config; in rcar_mmc_get_card_present()
1551 if (cfg->non_removable) { in rcar_mmc_get_card_present()
1560 /* JESD84-B51, 6.6.5.1 Sampling Tuning Sequence for HS200 */
1581 * In 4 bit mode the same pattern is used as shown above,
1583 * 8-bits pattern: 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00 ...
1585 * 4-bits pattern: 0xff 0x0f 0xff 0x00 ...
1613 int ret = -ENOTSUP; in rcar_mmc_execute_tuning()
1627 return -EINVAL; in rcar_mmc_execute_tuning()
1630 dev_data = dev->data; in rcar_mmc_execute_tuning()
1631 dev_data->can_retune = 0; in rcar_mmc_execute_tuning()
1633 if (dev_data->host_io.timing == SDHC_TIMING_HS200) { in rcar_mmc_execute_tuning()
1636 } else if (dev_data->host_io.timing != SDHC_TIMING_HS400) { in rcar_mmc_execute_tuning()
1639 LOG_ERR("%s: tuning isn't possible in HS400 mode, it should be done in HS200", in rcar_mmc_execute_tuning()
1640 dev->name); in rcar_mmc_execute_tuning()
1641 return -EINVAL; in rcar_mmc_execute_tuning()
1648 data.data = dev_data->tuning_buf; in rcar_mmc_execute_tuning()
1650 if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH4BIT) { in rcar_mmc_execute_tuning()
1653 } else if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) { in rcar_mmc_execute_tuning()
1657 LOG_ERR("%s: don't support tuning for 1-bit bus width", dev->name); in rcar_mmc_execute_tuning()
1658 return -EINVAL; in rcar_mmc_execute_tuning()
1685 * - one burn: 0b10000011 in rcar_mmc_execute_tuning()
1686 * - two burns: 0b1000001110000011 in rcar_mmc_execute_tuning()
1693 memset(dev_data->tuning_buf, 0, data.block_size); in rcar_mmc_execute_tuning()
1696 LOG_DBG("%s: received an error (%d) during tuning request", dev->name, ret); in rcar_mmc_execute_tuning()
1712 if (memcmp(tun_block_ptr, dev_data->tuning_buf, data.block_size)) { in rcar_mmc_execute_tuning()
1714 dev->name, tap_idx); in rcar_mmc_execute_tuning()
1720 LOG_DBG("%s: smpcmp_bitmask[%u] 0x%08x", dev->name, tap_idx, smpcmp_bitmask); in rcar_mmc_execute_tuning()
1733 LOG_ERR("%s: there isn't any valid tap during tuning", dev->name); in rcar_mmc_execute_tuning()
1742 if ((valid_taps >> RENESAS_TAPNUM) == (1 << RENESAS_TAPNUM) - 1) { in rcar_mmc_execute_tuning()
1753 if ((valid_taps >> RENESAS_TAPNUM) == (1 << RENESAS_TAPNUM) - 1) { in rcar_mmc_execute_tuning()
1756 if (!dev_data->manual_retuning) { in rcar_mmc_execute_tuning()
1759 dev_data->can_retune = 1; in rcar_mmc_execute_tuning()
1768 rsh = find_lsb_set(valid_taps) - 1; in rcar_mmc_execute_tuning()
1774 num_bits_in_range = find_lsb_set(~valid_taps) - 1; in rcar_mmc_execute_tuning()
1789 LOG_DBG("%s: valid_taps %08x smpcmp_bitmask %08x tap_idx %u", dev->name, valid_taps, in rcar_mmc_execute_tuning()
1792 if (!dev_data->manual_retuning) { in rcar_mmc_execute_tuning()
1795 dev_data->can_retune = 1; in rcar_mmc_execute_tuning()
1807 struct mmc_rcar_data *dev_data = dev->data; in rcar_mmc_retune_if_needed()
1813 if (!dev_data->can_retune) { in rcar_mmc_retune_if_needed()
1824 LOG_DBG("%s: scc_tapset %08x scc_rvsreq %08x request %d is manual tuning %d", dev->name, in rcar_mmc_retune_if_needed()
1825 scc_tapset, reg, request_retune, dev_data->manual_retuning); in rcar_mmc_retune_if_needed()
1827 if (request_retune || (scc_pos_err && !dev_data->manual_retuning)) { in rcar_mmc_retune_if_needed()
1835 scc_tapset = (scc_tapset - 1) % RENESAS_TAPNUM; in rcar_mmc_retune_if_needed()
1841 ret = -EINVAL; in rcar_mmc_retune_if_needed()
1842 LOG_ERR("%s: can't perform manual tuning SCC_RVSREQ %08x", dev->name, reg); in rcar_mmc_retune_if_needed()
1865 * @retval -EINVAL: some of pointers provided to the function are NULL
1871 if (!props || !dev || !dev->data) { in rcar_mmc_get_host_props()
1872 return -EINVAL; in rcar_mmc_get_host_props()
1875 data = dev->data; in rcar_mmc_get_host_props()
1876 memcpy(props, &data->props, sizeof(*props)); in rcar_mmc_get_host_props()
1892 /* start SD-IF clock at max frequency configured in dts */
1896 const struct device *cpg_dev = cfg->cpg_dev; in rcar_mmc_init_start_clk()
1897 uintptr_t rate = cfg->max_frequency; in rcar_mmc_init_start_clk()
1899 ret = clock_control_on(cpg_dev, (clock_control_subsys_t *)&cfg->bus_clk); in rcar_mmc_init_start_clk()
1904 ret = clock_control_on(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk); in rcar_mmc_init_start_clk()
1909 ret = clock_control_set_rate(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk, in rcar_mmc_init_start_clk()
1912 clock_control_off(cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk); in rcar_mmc_init_start_clk()
1916 ret = clock_control_set_rate(cpg_dev, (clock_control_subsys_t *)&cfg->bus_clk, in rcar_mmc_init_start_clk()
1926 struct mmc_rcar_data *data = dev->data; in rcar_mmc_init_host_props()
1927 const struct mmc_rcar_cfg *cfg = dev->config; in rcar_mmc_init_host_props()
1928 struct sdhc_host_props *props = &data->props; in rcar_mmc_init_host_props()
1929 struct sdhc_host_caps *host_caps = &props->host_caps; in rcar_mmc_init_host_props()
1935 props->f_max = cfg->max_frequency; in rcar_mmc_init_host_props()
1940 props->f_min = (cfg->max_frequency >> 9); in rcar_mmc_init_host_props()
1942 props->power_delay = 100; /* ms */ in rcar_mmc_init_host_props()
1944 props->is_spi = 0; in rcar_mmc_init_host_props()
1946 switch (cfg->bus_width) { in rcar_mmc_init_host_props()
1948 host_caps->bus_8_bit_support = 1; in rcar_mmc_init_host_props()
1950 host_caps->bus_4_bit_support = 1; in rcar_mmc_init_host_props()
1955 host_caps->high_spd_support = 1; in rcar_mmc_init_host_props()
1957 host_caps->sdr104_support = cfg->mmc_sdr104_support; in rcar_mmc_init_host_props()
1958 host_caps->sdr50_support = cfg->uhs_support; in rcar_mmc_init_host_props()
1959 /* neither Linux nor U-boot support DDR50 mode, that's why we don't support it too */ in rcar_mmc_init_host_props()
1960 host_caps->ddr50_support = 0; in rcar_mmc_init_host_props()
1961 host_caps->hs200_support = cfg->mmc_hs200_1_8v; in rcar_mmc_init_host_props()
1963 host_caps->hs400_support = 0; in rcar_mmc_init_host_props()
1966 host_caps->vol_330_support = in rcar_mmc_init_host_props()
1967 regulator_is_supported_voltage(cfg->regulator_vqmmc, 3300000, 3300000); in rcar_mmc_init_host_props()
1968 host_caps->vol_300_support = in rcar_mmc_init_host_props()
1969 regulator_is_supported_voltage(cfg->regulator_vqmmc, 3000000, 3000000); in rcar_mmc_init_host_props()
1970 host_caps->vol_180_support = in rcar_mmc_init_host_props()
1971 regulator_is_supported_voltage(cfg->regulator_vqmmc, 1800000, 1800000); in rcar_mmc_init_host_props()
1979 struct mmc_rcar_data *data = dev->data; in rcar_mmc_disable_scc()
1998 /* disable hs400 mode & data output timing */ in rcar_mmc_disable_scc()
2013 data->can_retune = 0; in rcar_mmc_disable_scc()
2023 struct mmc_rcar_data *data = dev->data; in rcar_mmc_init_controller_regs()
2043 /* set system address increment mode selector & 64-bit bus width */ in rcar_mmc_init_controller_regs()
2049 data->ver = rcar_mmc_read_reg32(dev, RCAR_MMC_VERSION); in rcar_mmc_init_controller_regs()
2050 data->ver &= RCAR_MMC_VERSION_IP; in rcar_mmc_init_controller_regs()
2068 * Read/write access to SD_BUF0 can be performed with the 64-bit access. in rcar_mmc_init_controller_regs()
2073 data->width_access_sd_buf0 = 8; in rcar_mmc_init_controller_regs()
2085 ios.clock = data->props.f_min; in rcar_mmc_init_controller_regs()
2088 data->restore_cfg_after_reset = 1; in rcar_mmc_init_controller_regs()
2102 struct mmc_rcar_data *data = dev->data; in rcar_mmc_irq_handler()
2106 k_sem_give(&data->irq_xref_fin); in rcar_mmc_irq_handler()
2108 LOG_WRN("%s: warning: non-dma event triggers irq", dev->name); in rcar_mmc_irq_handler()
2117 struct mmc_rcar_data *data = dev->data; in rcar_mmc_init()
2118 const struct mmc_rcar_cfg *cfg = dev->config; in rcar_mmc_init()
2121 ret = k_sem_init(&data->irq_xref_fin, 0, 1); in rcar_mmc_init()
2123 LOG_ERR("%s: can't init semaphore", dev->name); in rcar_mmc_init()
2131 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in rcar_mmc_init()
2133 LOG_ERR("%s: error can't apply pinctrl state", dev->name); in rcar_mmc_init()
2137 if (!device_is_ready(cfg->cpg_dev)) { in rcar_mmc_init()
2138 LOG_ERR("%s: error cpg_dev isn't ready", dev->name); in rcar_mmc_init()
2139 ret = -ENODEV; in rcar_mmc_init()
2145 LOG_ERR("%s: error can't turn on the cpg", dev->name); in rcar_mmc_init()
2158 cfg->irq_config_func(dev); in rcar_mmc_init()
2161 LOG_INF("%s: initialize driver, MMC version 0x%hhx", dev->name, data->ver); in rcar_mmc_init()
2166 clock_control_off(cfg->cpg_dev, (clock_control_subsys_t *)&cfg->cpg_clk); in rcar_mmc_init()
2170 k_mem_unmap_phys_bare((uint8_t *)DEVICE_MMIO_GET(dev), DEVICE_MMIO_ROM_PTR(dev)->size); in rcar_mmc_init()