Lines Matching full:3
15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
16 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
17 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
18 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
19 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
20 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
21 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
22 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
27 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
28 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
29 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
30 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
31 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
32 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
33 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
37 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
38 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
39 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
40 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
41 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
46 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
47 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
48 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
49 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
50 { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
51 { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
52 { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
53 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
57 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
58 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
59 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
60 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
61 { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
62 { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
63 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
64 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
68 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
69 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
70 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
71 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
72 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
73 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
74 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
75 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
79 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
87 { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
94 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
105 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
110 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
111 { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
112 { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
113 { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
114 { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
115 { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
116 { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
117 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
121 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
122 { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
123 { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
124 { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
125 { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
126 { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
127 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
128 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
132 { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
133 { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
134 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
139 { RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
140 { RCAR_GP_PIN(4, 6), 24, 3 }, /* GP4_06 */
141 { RCAR_GP_PIN(4, 5), 20, 3 }, /* GP4_05 */
142 { RCAR_GP_PIN(4, 4), 16, 3 }, /* GP4_04 */
143 { RCAR_GP_PIN(4, 3), 12, 3 }, /* GP4_03 */
144 { RCAR_GP_PIN(4, 2), 8, 3 }, /* GP4_02 */
145 { RCAR_GP_PIN(4, 1), 4, 3 }, /* GP4_01 */
146 { RCAR_GP_PIN(4, 0), 0, 3 }, /* GP4_00 */
150 { RCAR_GP_PIN(4, 15), 28, 3 }, /* GP4_15 */
151 { RCAR_GP_PIN(4, 14), 24, 3 }, /* GP4_14 */
152 { RCAR_GP_PIN(4, 13), 20, 3 }, /* GP4_13 */
153 { RCAR_GP_PIN(4, 12), 16, 3 }, /* GP4_12 */
154 { RCAR_GP_PIN(4, 11), 12, 3 }, /* GP4_11 */
155 { RCAR_GP_PIN(4, 10), 8, 3 }, /* GP4_10 */
156 { RCAR_GP_PIN(4, 9), 4, 3 }, /* GP4_09 */
157 { RCAR_GP_PIN(4, 8), 0, 3 }, /* GP4_08 */
161 { RCAR_GP_PIN(4, 23), 28, 3 }, /* MSPI0CSS1 */
162 { RCAR_GP_PIN(4, 22), 24, 3 }, /* MPSI0SO/MSPI0DCS */
163 { RCAR_GP_PIN(4, 21), 20, 3 }, /* MPSI0SI */
164 { RCAR_GP_PIN(4, 20), 16, 3 }, /* MSPI0SC */
165 { RCAR_GP_PIN(4, 19), 12, 3 }, /* GP4_19 */
166 { RCAR_GP_PIN(4, 18), 8, 3 }, /* GP4_18 */
167 { RCAR_GP_PIN(4, 17), 4, 3 }, /* GP4_17 */
168 { RCAR_GP_PIN(4, 16), 0, 3 }, /* GP4_16 */
172 { RCAR_GP_PIN(4, 30), 24, 3 }, /* MSPI1CSS1 */
173 { RCAR_GP_PIN(4, 29), 20, 3 }, /* MSPI1CSS2 */
174 { RCAR_GP_PIN(4, 28), 16, 3 }, /* MSPI1SC */
175 { RCAR_GP_PIN(4, 27), 12, 3 }, /* MSPI1CSS0 */
176 { RCAR_GP_PIN(4, 26), 8, 3 }, /* MPSI1SO/MSPI1DCS */
177 { RCAR_GP_PIN(4, 25), 4, 3 }, /* MSPI1SI */
178 { RCAR_GP_PIN(4, 24), 0, 3 }, /* MSPI0CSS0 */
182 { RCAR_GP_PIN(5, 7), 28, 3 }, /* ETNB0RXD3 */
183 { RCAR_GP_PIN(5, 6), 24, 3 }, /* ETNB0RXER */
184 { RCAR_GP_PIN(5, 5), 20, 3 }, /* ETNB0MDC */
185 { RCAR_GP_PIN(5, 4), 16, 3 }, /* ETNB0LINKSTA */
186 { RCAR_GP_PIN(5, 3), 12, 3 }, /* ETNB0WOL */
187 { RCAR_GP_PIN(5, 2), 8, 3 }, /* ETNB0MD */
188 { RCAR_GP_PIN(5, 1), 4, 3 }, /* RIIC0SDA */
189 { RCAR_GP_PIN(5, 0), 0, 3 }, /* RIIC0SCL */
193 { RCAR_GP_PIN(5, 15), 28, 3 }, /* ETNB0TXCLK */
194 { RCAR_GP_PIN(5, 14), 24, 3 }, /* ETNB0TXD3 */
195 { RCAR_GP_PIN(5, 13), 20, 3 }, /* ETNB0TXER */
196 { RCAR_GP_PIN(5, 12), 16, 3 }, /* ETNB0RXCLK */
197 { RCAR_GP_PIN(5, 11), 12, 3 }, /* ETNB0RXD0 */
198 { RCAR_GP_PIN(5, 10), 8, 3 }, /* ETNB0RXDV */
199 { RCAR_GP_PIN(5, 9), 4, 3 }, /* ETNB0RXD2 */
200 { RCAR_GP_PIN(5, 8), 0, 3 }, /* ETNB0RXD1 */
204 { RCAR_GP_PIN(5, 19), 12, 3 }, /* ETNB0TXD0 */
205 { RCAR_GP_PIN(5, 18), 8, 3 }, /* ETNB0TXEN */
206 { RCAR_GP_PIN(5, 17), 4, 3 }, /* ETNB0TXD2 */
207 { RCAR_GP_PIN(5, 16), 0, 3 }, /* ETNB0TXD1 */
212 { RCAR_GP_PIN(6, 7), 28, 3 }, /* RLIN34RX/INTP20 */
213 { RCAR_GP_PIN(6, 6), 24, 3 }, /* RLIN34TX */
214 { RCAR_GP_PIN(6, 5), 20, 3 }, /* RLIN35RX/INTP21 */
215 { RCAR_GP_PIN(6, 4), 16, 3 }, /* RLIN35TX */
216 { RCAR_GP_PIN(6, 3), 12, 3 }, /* RLIN36RX/INTP22 */
217 { RCAR_GP_PIN(6, 2), 8, 3 }, /* RLIN36TX */
218 { RCAR_GP_PIN(6, 1), 4, 3 }, /* RLIN37RX/INTP23 */
219 { RCAR_GP_PIN(6, 0), 0, 3 }, /* RLIN37TX */
223 { RCAR_GP_PIN(6, 15), 28, 3 }, /* RLIN30RX/INTP16 */
224 { RCAR_GP_PIN(6, 14), 24, 3 }, /* RLIN30TX */
225 { RCAR_GP_PIN(6, 13), 20, 3 }, /* RLIN31RX/INTP17 */
226 { RCAR_GP_PIN(6, 12), 16, 3 }, /* RLIN31TX */
227 { RCAR_GP_PIN(6, 11), 12, 3 }, /* RLIN32RX/INTP18 */
228 { RCAR_GP_PIN(6, 10), 8, 3 }, /* RLIN32TX */
229 { RCAR_GP_PIN(6, 9), 4, 3 }, /* RLIN33RX/INTP19 */
230 { RCAR_GP_PIN(6, 8), 0, 3 }, /* RLIN33TX */
234 { RCAR_GP_PIN(6, 22), 24, 3 }, /* NMI1 */
235 { RCAR_GP_PIN(6, 21), 20, 3 }, /* INTP32 */
236 { RCAR_GP_PIN(6, 20), 16, 3 }, /* INTP33 */
237 { RCAR_GP_PIN(6, 19), 12, 3 }, /* INTP34 */
238 { RCAR_GP_PIN(6, 18), 8, 3 }, /* INTP35 */
239 { RCAR_GP_PIN(6, 17), 4, 3 }, /* INTP36 */
240 { RCAR_GP_PIN(6, 16), 0, 3 }, /* INTP37 */
244 { RCAR_GP_PIN(6, 31), 28, 3 }, /* PRESETOUT1# */
248 { RCAR_GP_PIN(7, 7), 28, 3 }, /* CAN3RX/INTP3 */
249 { RCAR_GP_PIN(7, 6), 24, 3 }, /* CAN3TX */
250 { RCAR_GP_PIN(7, 5), 20, 3 }, /* CAN2RX/INTP2 */
251 { RCAR_GP_PIN(7, 4), 16, 3 }, /* CAN2TX */
252 { RCAR_GP_PIN(7, 3), 12, 3 }, /* CAN1RX/INTP1 */
253 { RCAR_GP_PIN(7, 2), 8, 3 }, /* CAN1TX */
254 { RCAR_GP_PIN(7, 1), 4, 3 }, /* CAN0RX/INTP0 */
255 { RCAR_GP_PIN(7, 0), 0, 3 }, /* CAN0TX */
259 { RCAR_GP_PIN(7, 15), 28, 3 }, /* CAN7RX/INTP7 */
260 { RCAR_GP_PIN(7, 14), 24, 3 }, /* CAN7TX */
261 { RCAR_GP_PIN(7, 13), 20, 3 }, /* CAN6RX/INTP6 */
262 { RCAR_GP_PIN(7, 12), 16, 3 }, /* CAN6TX */
263 { RCAR_GP_PIN(7, 11), 12, 3 }, /* CAN5RX/INTP5 */
264 { RCAR_GP_PIN(7, 10), 8, 3 }, /* CAN5TX */
265 { RCAR_GP_PIN(7, 9), 4, 3 }, /* CAN4RX/INTP4 */
266 { RCAR_GP_PIN(7, 8), 0, 3 }, /* CAN4TX */
270 { RCAR_GP_PIN(7, 23), 28, 3 }, /* CAN11RX/INTP11 */
271 { RCAR_GP_PIN(7, 22), 24, 3 }, /* CAN11TX */
272 { RCAR_GP_PIN(7, 21), 20, 3 }, /* CAN10RX/INTP10 */
273 { RCAR_GP_PIN(7, 20), 16, 3 }, /* CAN10TX */
274 { RCAR_GP_PIN(7, 19), 12, 3 }, /* CAN9RX/INTP9 */
275 { RCAR_GP_PIN(7, 18), 8, 3 }, /* CAN9TX */
276 { RCAR_GP_PIN(7, 17), 4, 3 }, /* CAN8RX/INTP8 */
277 { RCAR_GP_PIN(7, 16), 0, 3 }, /* CAN8TX */
281 { RCAR_GP_PIN(7, 31), 28, 3 }, /* CAN15RX/INTP15 */
282 { RCAR_GP_PIN(7, 30), 24, 3 }, /* CAN15TX */
283 { RCAR_GP_PIN(7, 29), 20, 3 }, /* CAN14RX/INTP14 */
284 { RCAR_GP_PIN(7, 28), 16, 3 }, /* CAN14TX */
285 { RCAR_GP_PIN(7, 27), 12, 3 }, /* CAN13RX/INTP13 */
286 { RCAR_GP_PIN(7, 26), 8, 3 }, /* CAN13TX */
287 { RCAR_GP_PIN(7, 25), 4, 3 }, /* CAN12RX/INTP12 */
288 { RCAR_GP_PIN(7, 24), 0, 3 }, /* CAN12TX */
292 { RCAR_GP_PIN(8, 0), 0, 3 }, /* PRESETOUT0# */
315 [3] = RCAR_GP_PIN(0, 3), /* HTX0 */
349 [3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
383 [3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
414 [0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
415 [1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
416 [2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
417 [3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
418 [4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
419 [5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
420 [6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
421 [7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
422 [8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
423 [9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
424 [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
425 [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
426 [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
427 [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
428 [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
429 [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
430 [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
431 [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
432 [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
451 [3] = RCAR_GP_PIN(4, 3), /* GP4_03 */
485 [3] = RCAR_GP_PIN(5, 3), /* ETNB0WOL */
519 [3] = RCAR_GP_PIN(6, 3), /* RLIN36RX/INTP22 */
553 [3] = RCAR_GP_PIN(7, 3), /* CAN1RX/INTP1 */