Lines Matching refs:base
24 #define MU(config) ((MU_Type *)config->base)
33 MU_Type *base; member
53 static inline bool MU_IsRxFull(MU_Type *base, uint32_t index) in MU_IsRxFull() argument
57 return (bool)(MU_GetStatusFlags(base) & kMU_Rx0FullFlag); in MU_IsRxFull()
59 return (bool)(MU_GetStatusFlags(base) & kMU_Rx1FullFlag); in MU_IsRxFull()
61 return (bool)(MU_GetStatusFlags(base) & kMU_Rx2FullFlag); in MU_IsRxFull()
63 return (bool)(MU_GetStatusFlags(base) & kMU_Rx3FullFlag); in MU_IsRxFull()
81 static inline bool MU_IsTxEmpty(MU_Type *base, uint32_t index) in MU_IsTxEmpty() argument
85 return (bool)(MU_GetStatusFlags(base) & kMU_Tx0EmptyFlag); in MU_IsTxEmpty()
87 return (bool)(MU_GetStatusFlags(base) & kMU_Tx1EmptyFlag); in MU_IsTxEmpty()
89 return (bool)(MU_GetStatusFlags(base) & kMU_Tx2EmptyFlag); in MU_IsTxEmpty()
91 return (bool)(MU_GetStatusFlags(base) & kMU_Tx3EmptyFlag); in MU_IsTxEmpty()
103 MU_Type *base = MU(config); in imx_mu_isr() local
111 status_reg = base->SR >>= MU_SR_RFn_SHIFT; in imx_mu_isr()
123 if (!MU_IsRxFull(base, in imx_mu_isr()
132 data32[i] = MU_ReceiveMsg(base, in imx_mu_isr()
135 MU_ReceiveMsg(base, in imx_mu_isr()
168 MU_Type *base = MU(config); in imx_mu_ipm_send() local
189 MU_SendMsgNonBlocking(base, id * IMX_IPM_DATA_REGS + i, in imx_mu_ipm_send()
192 while (!MU_IsTxEmpty(base, in imx_mu_ipm_send()
197 if (MU_IsTxEmpty(base, id * IMX_IPM_DATA_REGS + i)) { in imx_mu_ipm_send()
198 MU_SendMsg(base, id * IMX_IPM_DATA_REGS + i, in imx_mu_ipm_send()
208 status = MU_TrySendMsg(base, id * IMX_IPM_DATA_REGS + i, in imx_mu_ipm_send()
216 while (!MU_IsTxEmpty(base, in imx_mu_ipm_send()
252 MU_Type *base = MU(config); in imx_mu_ipm_set_enabled() local
256 MU_EnableInterrupts(base, kMU_Rx0FullInterruptEnable); in imx_mu_ipm_set_enabled()
257 MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable); in imx_mu_ipm_set_enabled()
258 MU_EnableInterrupts(base, kMU_Rx2FullInterruptEnable); in imx_mu_ipm_set_enabled()
259 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
261 MU_DisableInterrupts(base, kMU_Rx0FullInterruptEnable); in imx_mu_ipm_set_enabled()
262 MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable); in imx_mu_ipm_set_enabled()
263 MU_DisableInterrupts(base, kMU_Rx2FullInterruptEnable); in imx_mu_ipm_set_enabled()
264 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
268 MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable); in imx_mu_ipm_set_enabled()
269 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
271 MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable); in imx_mu_ipm_set_enabled()
272 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
276 MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
278 MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable); in imx_mu_ipm_set_enabled()
286 MU_EnableRxFullInt(base, 0U); in imx_mu_ipm_set_enabled()
287 MU_EnableRxFullInt(base, 1U); in imx_mu_ipm_set_enabled()
288 MU_EnableRxFullInt(base, 2U); in imx_mu_ipm_set_enabled()
289 MU_EnableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
291 MU_DisableRxFullInt(base, 0U); in imx_mu_ipm_set_enabled()
292 MU_DisableRxFullInt(base, 1U); in imx_mu_ipm_set_enabled()
293 MU_DisableRxFullInt(base, 2U); in imx_mu_ipm_set_enabled()
294 MU_DisableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
298 MU_EnableRxFullInt(base, 1U); in imx_mu_ipm_set_enabled()
299 MU_EnableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
301 MU_DisableRxFullInt(base, 1U); in imx_mu_ipm_set_enabled()
302 MU_DisableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
306 MU_EnableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
308 MU_DisableRxFullInt(base, 3U); in imx_mu_ipm_set_enabled()
333 MU_Type * base = MU(config); in imx_mu_init() local
335 MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | in imx_mu_init()
357 .base = (MU_Type *)DT_INST_REG_ADDR(0),