59 	uint32_t line = rv32m1_intmux_line(irq);  in rv32m1_intmux_irq_enable()  local
61 	regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line);  in rv32m1_intmux_irq_enable()
68 	uint32_t line = rv32m1_intmux_line(irq);  in rv32m1_intmux_irq_disable()  local
70 	regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line);  in rv32m1_intmux_irq_disable()
92 	uint32_t line = rv32m1_intmux_line(irq);  in rv32m1_intmux_get_line_state()  local
94 	if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) {  in rv32m1_intmux_get_line_state()
105 #define ISR_ENTRY(channel, line) \  argument
106 	((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
114 	uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2);  in rv32m1_intmux_isr()  local
126 	if (line < VECN_OFFSET) {  in rv32m1_intmux_isr()
130 	entry = &isr_base[ISR_ENTRY(channel, (line - VECN_OFFSET))];  in rv32m1_intmux_isr()