Lines Matching full:i2c
10 #include <zephyr/drivers/i2c.h>
75 mxc_i2c_regs_t *i2c = cfg->regs; in api_configure() local
78 case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */ in api_configure()
79 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE); in api_configure()
82 case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */ in api_configure()
83 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED); in api_configure()
87 case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */ in api_configure()
88 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED); in api_configure()
93 case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */ in api_configure()
94 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED); in api_configure()
111 mxc_i2c_regs_t *i2c = config->regs; in api_target_register() local
116 ret = MXC_I2C_Init(i2c, 0, cfg->address); in api_target_register()
120 MXC_I2C_SlaveTransactionAsync(i2c, NULL); in api_target_register()
130 mxc_i2c_regs_t *i2c = config->regs; in api_target_unregister() local
139 return MXC_I2C_Init(i2c, 1, 0); in api_target_unregister()
142 static int i2c_max32_target_callback(const struct device *dev, mxc_i2c_regs_t *i2c, in i2c_max32_target_callback() argument
160 rxcnt = MXC_I2C_GetRXFIFOAvailable(i2c); in i2c_max32_target_callback()
163 MXC_I2C_ReadRXFIFO(i2c, &rxval, 1); in i2c_max32_target_callback()
167 MXC_I2C_ClearRXFIFO(i2c); in i2c_max32_target_callback()
174 MXC_I2C_WriteTXFIFO(i2c, &txval, 1); in i2c_max32_target_callback()
196 mxc_i2c_regs_t *i2c = cfg->regs; in api_recover_bus() local
198 ret = MXC_I2C_Recover(i2c, I2C_RECOVER_MAX_RETRIES); in api_recover_bus()
204 static int i2c_max32_transfer_sync(mxc_i2c_regs_t *i2c, struct max32_i2c_data *data) in i2c_max32_transfer_sync() argument
213 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
223 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
225 data->written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[data->written], in i2c_max32_transfer_sync()
227 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_TX_THD, 0); in i2c_max32_transfer_sync()
235 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0); in i2c_max32_transfer_sync()
236 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len); in i2c_max32_transfer_sync()
238 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
240 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb); in i2c_max32_transfer_sync()
241 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_RX_THD, 0); in i2c_max32_transfer_sync()
248 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
250 MXC_I2C_GetRXFIFOAvailable(i2c) == 0) { in i2c_max32_transfer_sync()
251 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb); in i2c_max32_transfer_sync()
252 Wrap_MXC_I2C_Restart(i2c); in i2c_max32_transfer_sync()
253 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0); in i2c_max32_transfer_sync()
254 i2c->fifo = (req->addr << 1) | 0x1; in i2c_max32_transfer_sync()
258 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
264 MXC_I2C_Stop(i2c); in i2c_max32_transfer_sync()
266 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
272 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
275 while (Wrap_MXC_I2C_GetTxFIFOLevel(i2c) > 0) { in i2c_max32_transfer_sync()
276 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_transfer_sync()
279 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_transfer_sync()
368 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer_dma() local
374 MXC_I2C_SetRXThreshold(i2c, 1); in i2c_max32_transfer_dma()
375 MXC_I2C_SetTXThreshold(i2c, 2); in i2c_max32_transfer_dma()
376 MXC_I2C_ClearTXFIFO(i2c); in i2c_max32_transfer_dma()
377 MXC_I2C_ClearRXFIFO(i2c); in i2c_max32_transfer_dma()
383 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1); in i2c_max32_transfer_dma()
384 Wrap_MXC_I2C_SetRxCount(i2c, msgs[i].len); in i2c_max32_transfer_dma()
391 i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0); in i2c_max32_transfer_dma()
392 i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN; in i2c_max32_transfer_dma()
395 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1); in i2c_max32_transfer_dma()
402 i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0); in i2c_max32_transfer_dma()
403 i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN; in i2c_max32_transfer_dma()
407 Wrap_MXC_I2C_Start(i2c); in i2c_max32_transfer_dma()
409 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0); in i2c_max32_transfer_dma()
410 i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN); in i2c_max32_transfer_dma()
416 MXC_I2C_Stop(i2c); in i2c_max32_transfer_dma()
435 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer() local
440 req->i2c = i2c; in i2c_max32_transfer()
445 MXC_I2C_ClearRXFIFO(i2c); in i2c_max32_transfer()
446 MXC_I2C_ClearTXFIFO(i2c); in i2c_max32_transfer()
447 MXC_I2C_SetRXThreshold(i2c, 1); in i2c_max32_transfer()
482 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_transfer()
483 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0); in i2c_max32_transfer()
484 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len); in i2c_max32_transfer()
486 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in i2c_max32_transfer()
487 MXC_I2C_Start(i2c); in i2c_max32_transfer()
488 Wrap_MXC_I2C_WaitForRestart(i2c); in i2c_max32_transfer()
489 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1); in i2c_max32_transfer()
492 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1); in i2c_max32_transfer()
493 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in i2c_max32_transfer()
495 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0); in i2c_max32_transfer()
501 MXC_I2C_Stop(i2c); in i2c_max32_transfer()
506 while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) { in i2c_max32_transfer()
508 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, in i2c_max32_transfer()
528 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer() local
533 req->i2c = i2c; in i2c_max32_transfer()
538 MXC_I2C_ClearRXFIFO(i2c); in i2c_max32_transfer()
572 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_transfer()
574 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0); in i2c_max32_transfer()
576 MXC_I2C_Start(i2c); in i2c_max32_transfer()
577 Wrap_MXC_I2C_WaitForRestart(i2c); in i2c_max32_transfer()
578 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1); in i2c_max32_transfer()
580 ret = i2c_max32_transfer_sync(i2c, data); in i2c_max32_transfer()
582 MXC_I2C_Stop(i2c); in i2c_max32_transfer()
607 static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c) in i2c_max32_isr_target() argument
615 ctrl = i2c->ctrl; in i2c_max32_isr_target()
616 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); in i2c_max32_isr_target()
617 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_isr_target()
618 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_isr_target()
622 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP); in i2c_max32_isr_target()
624 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_isr_target()
625 MXC_I2C_ClearTXFIFO(i2c); in i2c_max32_isr_target()
626 MXC_I2C_ClearRXFIFO(i2c); in i2c_max32_isr_target()
632 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_RX_THRESH); in i2c_max32_isr_target()
636 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_OVERFLOW); in i2c_max32_isr_target()
644 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TX_THRESH); in i2c_max32_isr_target()
648 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_UNDERFLOW); in i2c_max32_isr_target()
654 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP); in i2c_max32_isr_target()
662 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP); in i2c_max32_isr_target()
675 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { in i2c_max32_isr_target()
677 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD); in i2c_max32_isr_target()
684 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_WR); in i2c_max32_isr_target()
691 Wrap_MXC_I2C_SetIntEn(i2c, int_en0, int_en1); in i2c_max32_isr_target()
696 static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c) in i2c_max32_isr_controller() argument
708 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); in i2c_max32_isr_controller()
709 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_isr_controller()
710 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_isr_controller()
711 txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c); in i2c_max32_isr_controller()
715 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0); in i2c_max32_isr_controller()
721 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in i2c_max32_isr_controller()
723 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in i2c_max32_isr_controller()
726 i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
733 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written], in i2c_max32_isr_controller()
738 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in i2c_max32_isr_controller()
740 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
742 Wrap_MXC_I2C_Stop(i2c); in i2c_max32_isr_controller()
749 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
754 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb); in i2c_max32_isr_controller()
756 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0); in i2c_max32_isr_controller()
758 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
759 Wrap_MXC_I2C_Stop(i2c); in i2c_max32_isr_controller()
763 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
770 i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE), in i2c_max32_isr_controller()
772 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb); in i2c_max32_isr_controller()
773 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in i2c_max32_isr_controller()
774 i2c->fifo = (req->addr << 1) | 0x1; in i2c_max32_isr_controller()
775 Wrap_MXC_I2C_Restart(i2c); in i2c_max32_isr_controller()
785 static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c) in i2c_max32_isr_controller_dma() argument
791 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); in i2c_max32_isr_controller_dma()
792 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_isr_controller_dma()
793 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_isr_controller_dma()
797 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0); in i2c_max32_isr_controller_dma()
812 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_isr() local
818 i2c_max32_isr_controller_dma(dev, i2c); in i2c_max32_isr()
822 i2c_max32_isr_controller(dev, i2c); in i2c_max32_isr()
829 i2c_max32_isr_target(dev, i2c); in i2c_max32_isr()
835 static DEVICE_API(i2c, api) = {
852 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_init() local
859 MXC_I2C_Shutdown(i2c); /* Clear everything out */ in i2c_max32_init()
871 ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */ in i2c_max32_init()
876 MXC_I2C_SetFrequency(i2c, cfg->bitrate); in i2c_max32_init()