Lines Matching +full:fast +full:- +full:plus
4 * SPDX-License-Identifier: Apache-2.0
74 const struct max32_i2c_config *const cfg = dev->config; in api_configure()
75 mxc_i2c_regs_t *i2c = cfg->regs; in api_configure()
82 case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */ in api_configure()
87 case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */ in api_configure()
100 return -ENOTSUP; in api_configure()
109 const struct max32_i2c_config *config = dev->config; in api_target_register()
110 struct max32_i2c_data *data = dev->data; in api_target_register()
111 mxc_i2c_regs_t *i2c = config->regs; in api_target_register()
114 data->target_cfg = cfg; in api_target_register()
116 ret = MXC_I2C_Init(i2c, 0, cfg->address); in api_target_register()
118 data->target_mode = 1; in api_target_register()
119 irq_enable(config->irqn); in api_target_register()
128 const struct max32_i2c_config *config = dev->config; in api_target_unregister()
129 struct max32_i2c_data *data = dev->data; in api_target_unregister()
130 mxc_i2c_regs_t *i2c = config->regs; in api_target_unregister()
132 data->target_cfg = NULL; in api_target_unregister()
133 data->target_mode = 0; in api_target_unregister()
136 irq_disable(config->irqn); in api_target_unregister()
145 struct max32_i2c_data *data = dev->data; in i2c_max32_target_callback()
146 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks; in i2c_max32_target_callback()
151 if (data->first_write && target_cb->write_requested) { in i2c_max32_target_callback()
152 target_cb->write_requested(data->target_cfg); in i2c_max32_target_callback()
153 data->first_write = false; in i2c_max32_target_callback()
161 if (target_cb->write_received) { in i2c_max32_target_callback()
162 while (rxcnt--) { in i2c_max32_target_callback()
164 target_cb->write_received(data->target_cfg, rxval); in i2c_max32_target_callback()
172 if (target_cb->read_requested) { in i2c_max32_target_callback()
173 target_cb->read_requested(data->target_cfg, &txval); in i2c_max32_target_callback()
176 if (target_cb->read_processed) { in i2c_max32_target_callback()
177 target_cb->read_processed(data->target_cfg, &txval); in i2c_max32_target_callback()
181 if (target_cb->stop) { in i2c_max32_target_callback()
182 target_cb->stop(data->target_cfg); in i2c_max32_target_callback()
184 data->first_write = true; in i2c_max32_target_callback()
195 const struct max32_i2c_config *const cfg = dev->config; in api_recover_bus()
196 mxc_i2c_regs_t *i2c = cfg->regs; in api_recover_bus()
208 mxc_i2c_req_t *req = &data->req; in i2c_max32_transfer_sync()
211 if (data->flags & (I2C_MSG_RESTART | I2C_MSG_READ)) { in i2c_max32_transfer_sync()
219 return -EIO; in i2c_max32_transfer_sync()
222 while (req->tx_len > data->written) { in i2c_max32_transfer_sync()
225 data->written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[data->written], in i2c_max32_transfer_sync()
226 req->tx_len - data->written); in i2c_max32_transfer_sync()
231 return -EIO; in i2c_max32_transfer_sync()
236 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len); in i2c_max32_transfer_sync()
237 while (req->rx_len > readb) { in i2c_max32_transfer_sync()
240 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb); in i2c_max32_transfer_sync()
245 return -EIO; in i2c_max32_transfer_sync()
249 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) && (req->rx_len > readb) && in i2c_max32_transfer_sync()
251 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb); in i2c_max32_transfer_sync()
254 i2c->fifo = (req->addr << 1) | 0x1; in i2c_max32_transfer_sync()
260 return -EIO; in i2c_max32_transfer_sync()
263 if (data->flags & I2C_MSG_STOP) { in i2c_max32_transfer_sync()
270 if (req->rx_len) { in i2c_max32_transfer_sync()
290 const struct device *i2c_dev = data->dev; in i2c_max32_dma_callback()
291 const struct max32_i2c_config *const cfg = i2c_dev->config; in i2c_max32_dma_callback()
294 data->err = -EIO; in i2c_max32_dma_callback()
296 if (data->req.restart) { in i2c_max32_dma_callback()
297 Wrap_MXC_I2C_Restart(cfg->regs); in i2c_max32_dma_callback()
299 Wrap_MXC_I2C_Stop(cfg->regs); in i2c_max32_dma_callback()
307 const struct max32_i2c_config *config = dev->config; in i2c_max32_tx_dma_load()
308 struct max32_i2c_data *data = dev->data; in i2c_max32_tx_dma_load()
315 dma_cfg.dma_slot = config->tx_dma.slot; in i2c_max32_tx_dma_load()
321 dma_blk.block_size = msg->len; in i2c_max32_tx_dma_load()
323 dma_blk.source_address = (uint32_t)msg->buf; in i2c_max32_tx_dma_load()
325 ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg); in i2c_max32_tx_dma_load()
330 return dma_start(config->tx_dma.dev, config->tx_dma.channel); in i2c_max32_tx_dma_load()
336 const struct max32_i2c_config *config = dev->config; in i2c_max32_rx_dma_load()
337 struct max32_i2c_data *data = dev->data; in i2c_max32_rx_dma_load()
344 dma_cfg.dma_slot = config->rx_dma.slot; in i2c_max32_rx_dma_load()
350 dma_blk.block_size = msg->len; in i2c_max32_rx_dma_load()
352 dma_blk.dest_address = (uint32_t)msg->buf; in i2c_max32_rx_dma_load()
354 ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg); in i2c_max32_rx_dma_load()
359 return dma_start(config->rx_dma.dev, config->rx_dma.channel); in i2c_max32_rx_dma_load()
366 const struct max32_i2c_config *const cfg = dev->config; in i2c_max32_transfer_dma()
367 struct max32_i2c_data *data = dev->data; in i2c_max32_transfer_dma()
368 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer_dma()
372 k_sem_take(&data->lock, K_FOREVER); in i2c_max32_transfer_dma()
380 data->req.restart = !(msgs[i].flags & I2C_MSG_STOP); in i2c_max32_transfer_dma()
392 i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN; in i2c_max32_transfer_dma()
403 i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN; in i2c_max32_transfer_dma()
405 data->err = 0; in i2c_max32_transfer_dma()
408 ret = k_sem_take(&data->xfer, K_FOREVER); in i2c_max32_transfer_dma()
410 i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN); in i2c_max32_transfer_dma()
412 if (data->err) { in i2c_max32_transfer_dma()
413 ret = data->err; in i2c_max32_transfer_dma()
417 dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel); in i2c_max32_transfer_dma()
418 dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel); in i2c_max32_transfer_dma()
422 k_sem_give(&data->lock); in i2c_max32_transfer_dma()
433 const struct max32_i2c_config *const cfg = dev->config; in i2c_max32_transfer()
434 struct max32_i2c_data *data = dev->data; in i2c_max32_transfer()
435 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer()
436 mxc_i2c_req_t *req = &data->req; in i2c_max32_transfer()
440 req->i2c = i2c; in i2c_max32_transfer()
441 req->addr = target_address; in i2c_max32_transfer()
443 k_sem_take(&data->lock, K_FOREVER); in i2c_max32_transfer()
454 req->rx_buf = (unsigned char *)msgs[i].buf; in i2c_max32_transfer()
455 req->rx_len = msgs[i].len; in i2c_max32_transfer()
456 req->tx_buf = NULL; in i2c_max32_transfer()
457 req->tx_len = 0; in i2c_max32_transfer()
460 req->tx_buf = (unsigned char *)msgs[i].buf; in i2c_max32_transfer()
461 req->tx_len = msgs[i].len; in i2c_max32_transfer()
462 req->rx_buf = NULL; in i2c_max32_transfer()
463 req->rx_len = 0; in i2c_max32_transfer()
472 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) { in i2c_max32_transfer()
477 data->flags = msgs[i].flags; in i2c_max32_transfer()
478 data->readb = 0; in i2c_max32_transfer()
479 data->written = 0; in i2c_max32_transfer()
480 data->err = 0; in i2c_max32_transfer()
484 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len); in i2c_max32_transfer()
485 if ((data->flags & I2C_MSG_RESTART)) { in i2c_max32_transfer()
491 if (req->tx_len) { in i2c_max32_transfer()
492 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1); in i2c_max32_transfer()
499 ret = k_sem_take(&data->xfer, K_FOREVER); in i2c_max32_transfer()
500 if (data->err) { in i2c_max32_transfer()
502 ret = data->err; in i2c_max32_transfer()
504 if (data->flags & I2C_MSG_STOP) { in i2c_max32_transfer()
506 while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) { in i2c_max32_transfer()
517 k_sem_give(&data->lock); in i2c_max32_transfer()
526 const struct max32_i2c_config *const cfg = dev->config; in i2c_max32_transfer()
527 struct max32_i2c_data *data = dev->data; in i2c_max32_transfer()
528 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer()
529 mxc_i2c_req_t *req = &data->req; in i2c_max32_transfer()
533 req->i2c = i2c; in i2c_max32_transfer()
534 req->addr = target_address; in i2c_max32_transfer()
536 k_sem_take(&data->lock, K_FOREVER); in i2c_max32_transfer()
545 req->rx_buf = (unsigned char *)msgs[i].buf; in i2c_max32_transfer()
546 req->rx_len = msgs[i].len; in i2c_max32_transfer()
547 req->tx_buf = NULL; in i2c_max32_transfer()
548 req->tx_len = 0; in i2c_max32_transfer()
551 req->tx_buf = (unsigned char *)msgs[i].buf; in i2c_max32_transfer()
552 req->tx_len = msgs[i].len; in i2c_max32_transfer()
553 req->rx_buf = NULL; in i2c_max32_transfer()
554 req->rx_len = 0; in i2c_max32_transfer()
563 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) { in i2c_max32_transfer()
568 data->flags = msgs[i].flags; in i2c_max32_transfer()
569 data->readb = 0; in i2c_max32_transfer()
570 data->written = 0; in i2c_max32_transfer()
575 if (data->flags & I2C_MSG_RESTART) { in i2c_max32_transfer()
587 k_sem_give(&data->lock); in i2c_max32_transfer()
597 const struct max32_i2c_config *cfg = dev->config; in api_transfer()
599 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) { in api_transfer()
615 ctrl = i2c->ctrl; in i2c_max32_isr_target()
665 /* Restart detected, re-arm address match interrupt */ in i2c_max32_isr_target()
675 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { in i2c_max32_isr_target()
698 struct max32_i2c_data *data = dev->data; in i2c_max32_isr_controller()
699 mxc_i2c_req_t *req = &data->req; in i2c_max32_isr_controller()
705 written = data->written; in i2c_max32_isr_controller()
706 readb = data->readb; in i2c_max32_isr_controller()
714 data->err = -EIO; in i2c_max32_isr_controller()
716 k_sem_give(&data->xfer); in i2c_max32_isr_controller()
722 if (written < req->tx_len) { in i2c_max32_isr_controller()
724 } else if (readb < req->rx_len) { in i2c_max32_isr_controller()
730 if (req->tx_len && in i2c_max32_isr_controller()
732 if (written < req->tx_len) { in i2c_max32_isr_controller()
733 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written], in i2c_max32_isr_controller()
734 req->tx_len - written); in i2c_max32_isr_controller()
739 if (data->flags & I2C_MSG_STOP) { in i2c_max32_isr_controller()
744 k_sem_give(&data->xfer); in i2c_max32_isr_controller()
750 k_sem_give(&data->xfer); in i2c_max32_isr_controller()
754 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb); in i2c_max32_isr_controller()
755 if (readb == req->rx_len) { in i2c_max32_isr_controller()
757 if (data->flags & I2C_MSG_STOP) { in i2c_max32_isr_controller()
760 k_sem_give(&data->xfer); in i2c_max32_isr_controller()
764 k_sem_give(&data->xfer); in i2c_max32_isr_controller()
772 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb); in i2c_max32_isr_controller()
774 i2c->fifo = (req->addr << 1) | 0x1; in i2c_max32_isr_controller()
779 data->written = written; in i2c_max32_isr_controller()
780 data->readb = readb; in i2c_max32_isr_controller()
787 struct max32_i2c_data *data = dev->data; in i2c_max32_isr_controller_dma()
796 data->err = -EIO; in i2c_max32_isr_controller_dma()
798 k_sem_give(&data->xfer); in i2c_max32_isr_controller_dma()
800 if (!data->err && (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) { in i2c_max32_isr_controller_dma()
801 k_sem_give(&data->xfer); in i2c_max32_isr_controller_dma()
810 const struct max32_i2c_config *cfg = dev->config; in i2c_max32_isr()
811 struct max32_i2c_data *data = dev->data; in i2c_max32_isr()
812 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_isr()
815 if (data->target_mode == 0) { in i2c_max32_isr()
817 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) { in i2c_max32_isr()
828 if (data->target_mode == 1) { in i2c_max32_isr()
850 const struct max32_i2c_config *const cfg = dev->config; in i2c_max32_init()
851 struct max32_i2c_data *data = dev->data; in i2c_max32_init()
852 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_init()
855 if (!device_is_ready(cfg->clock)) { in i2c_max32_init()
856 return -ENODEV; in i2c_max32_init()
861 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk); in i2c_max32_init()
866 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT); in i2c_max32_init()
876 MXC_I2C_SetFrequency(i2c, cfg->bitrate); in i2c_max32_init()
878 k_sem_init(&data->lock, 1, 1); in i2c_max32_init()
881 cfg->irq_config_func(dev); in i2c_max32_init()
885 irq_enable(cfg->irqn); in i2c_max32_init()
887 k_sem_init(&data->xfer, 0, 1); in i2c_max32_init()
891 data->first_write = true; in i2c_max32_init()
892 data->target_mode = 0; in i2c_max32_init()
894 data->dev = dev; in i2c_max32_init()