Lines Matching full:1
34 #define MAX149x6_ADDR_MASK GENMASK(4, 1)
43 #define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x)))
47 #define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x)))
54 MAX14906_ADDR_1, /* A0=1, A1=0 */
55 MAX14906_ADDR_2, /* A0=0, A1=1 */
56 MAX14906_ADDR_3, /* A0=1, A1=1 */
96 uint8_t VDDOK_FAULT1: 1; /* BIT0 */
97 uint8_t VDDOK_FAULT2: 1;
98 uint8_t VDDOK_FAULT3: 1;
99 uint8_t VDDOK_FAULT4: 1;
100 uint8_t SAFE_DAMAGE_F1: 1;
101 uint8_t SAFE_DAMAGE_F2: 1;
102 uint8_t SAFE_DAMAGE_F3: 1;
103 uint8_t SAFE_DAMAGE_F4: 1; /* BIT7 */
110 uint8_t OVER_LD_FAULT: 1; /* BIT0 */
111 uint8_t CURR_LIM: 1;
112 uint8_t OW_OFF_FAULT: 1;
113 uint8_t ABOVE_VDD_FAULT: 1;
114 uint8_t SHT_VDD_FAULT: 1;
115 uint8_t DE_MAG_FAULT: 1;
116 uint8_t SUPPLY_ERR: 1;
117 uint8_t COM_ERR: 1; /* BIT7 */
124 uint8_t OVL1: 1; /* BIT0 */
125 uint8_t OVL2: 1;
126 uint8_t OVL3: 1;
127 uint8_t OVL4: 1;
128 uint8_t CL1: 1;
129 uint8_t CL2: 1;
130 uint8_t CL3: 1;
131 uint8_t CL4: 1; /* BIT7 */
138 uint8_t OW_OFF1: 1; /* BIT0 */
139 uint8_t OW_OFF2: 1;
140 uint8_t OW_OFF3: 1;
141 uint8_t OW_OFF4: 1;
142 uint8_t ABOVE_VDD1: 1;
143 uint8_t ABOVE_VDD2: 1;
144 uint8_t ABOVE_VDD3: 1;
145 uint8_t ABOVE_VDD4: 1; /* BIT7 */
152 uint8_t SHVDD1: 1; /* BIT0 */
153 uint8_t SHVDD2: 1;
154 uint8_t SHVDD3: 1;
155 uint8_t SHVDD4: 1;
156 uint8_t VDDOV1: 1;
157 uint8_t VDDOV2: 1;
158 uint8_t VDDOV3: 1;
159 uint8_t VDDOV4: 1; /* BIT7 */
166 uint8_t VINT_UV: 1; /* BIT0 */
167 uint8_t V5_UVLO: 1;
168 uint8_t VDD_LOW: 1;
169 uint8_t VDD_WARN: 1;
170 uint8_t VDD_UVLO: 1;
171 uint8_t THRMSHUTD: 1;
172 uint8_t LOSSGND: 1;
173 uint8_t WDOG_ERR: 1; /* BIT7 */
180 uint8_t OW_OFF_EN1: 1; /* BIT0 */
181 uint8_t OW_OFF_EN2: 1;
182 uint8_t OW_OFF_EN3: 1;
183 uint8_t OW_OFF_EN4: 1;
184 uint8_t GDRV_EN1: 1;
185 uint8_t GDRV_EN2: 1;
186 uint8_t GDRV_EN3: 1;
187 uint8_t GDRV_EN4: 1; /* BIT7 */
194 uint8_t SH_VDD_EN1: 1; /* BIT0 */
195 uint8_t SH_VDD_EN2: 1;
196 uint8_t SH_VDD_EN3: 1;
197 uint8_t SH_VDD_EN4: 1;
198 uint8_t VDD_OV_EN1: 1;
199 uint8_t VDD_OV_EN2: 1;
200 uint8_t VDD_OV_EN3: 1;
201 uint8_t VDD_OV_EN4: 1; /* BIT7 */
209 uint8_t OVL_STRETCH_EN: 1;
210 uint8_t ABOVE_VDD_PROT_EN: 1;
211 uint8_t VDD_FAULT_SEL: 1;
212 uint8_t VDD_FAULT_DIS: 1;
213 uint8_t RESERVED: 1;
214 uint8_t TYP_2_DI: 1; /* BIT7 */
241 uint8_t OVER_LD_M: 1; /* BIT0 */
242 uint8_t CURR_LIM_M: 1;
243 uint8_t OW_OFF_M: 1;
244 uint8_t ABOVE_VDD_M: 1;
245 uint8_t SHT_VDD_M: 1;
246 uint8_t VDD_OK_M: 1;
247 uint8_t SUPPLY_ERR_M: 1;
248 uint8_t COM_ERR_M: 1; /* BIT7 */
255 uint8_t FLED_SET: 1; /* BIT0 */
256 uint8_t SLED_SET: 1;
258 uint8_t FFILTER_EN: 1;
259 uint8_t FILTER_LONG: 1;
260 uint8_t FLATCH_EN: 1;
261 uint8_t LED_CURR_LIM: 1; /* BIT7 */
268 uint8_t VDD_ON_THR: 1; /* BIT0 */
269 uint8_t SYNCH_WD_EN: 1;
277 #define MAX149x6_SLED_MASK BIT(1)
281 #define MAX149x6_ENABLE 1