Lines Matching +full:address +full:- +full:0
4 * SPDX-License-Identifier: Apache-2.0
7 /* Port 0~4 PHY Control Register. */
8 #define PORTX_PHY_CONTROL_REGISTER 0x0u
10 #define MODE_10_BASET_HALF_DUPLEX 0x0u
12 #define MODE_10_BASET_FULL_DUPLEX 0x100u
14 #define MODE_100_BASET_HALF_DUPLEX 0x2000u
16 #define MODE_100_BASET_FULL_DUPLEX 0x2100u
26 /* Port 0~4 Status Data Register. */
27 #define PORTX_SWITCH_STATUS 0x10u
29 #define SPEED_10MBPS_HALF_DUPLEX 0x00u
31 #define SPEED_10MBPS_FULL_DUPLEX 0x01u
33 #define SPEED_100MBPS_HALF_DUPLEX 0x02u
35 #define SPEED_100MBPS_FULL_DUPLEX 0x03u
37 #define SPEED_AND_DUPLEX_OFFSET 0x01u
39 #define SPEED_AND_DUPLEX_MASK 0x07u
41 #define LINK_STATUS_MASK 0x1u
44 /* Address Table Control And Status Register PHY Address */
45 #define ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u
46 /* Address Table Control And Status Register Register SAddress */
47 #define ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u
49 /* Address Table Access bussy flag offset */
50 #define ATB_S_OFFSET 0xf
51 /* Address Table Command Result flag offset */
52 #define ATB_CR_OFFSET 0xd
53 /* Address Table Command Result flag mask */
54 #define ATB_CR_MASK 0x3
56 /* Unicast Address Table Index*/
57 #define UNICAST_ADDR_TAB (1 << 0 | 1 << 1)
58 /* Multicast Address Table Index*/
59 #define MULTICAST_ADDR_TAB (1 << 0)
63 /* Read a entry with sequence number of address table */
65 /* Write a entry with MAC address */
67 /* Delete a entry with MAC address */
69 /* Search a entry with MAC address */
74 /* Address Table Data 0 PHY Address */
75 #define ADDR_TAB_DATA0_PHY_ADDR 0x15u
76 /* Address Table Data 0 Register Address */
77 #define ADDR_TAB_DATA0_REG_ADDR 0x11u
79 #define ATB_PORT_MASK 0x1f
81 /* Address Table Data 1 PHY Address */
82 #define ADDR_TAB_DATA1_PHY_ADDR 0x15u
83 /* Address Table Data 1 Register Address */
84 #define ADDR_TAB_DATA1_REG_ADDR 0x12u
86 /* Address Table Data 2 PHY Address */
87 #define ADDR_TAB_DATA2_PHY_ADDR 0x15u
88 /* Address Table Data 2 Register Address */
89 #define ADDR_TAB_DATA2_REG_ADDR 0x13u
91 /* Address Table Data 3 PHY Address */
92 #define ADDR_TAB_DATA3_PHY_ADDR 0x15u
93 /* Address Table Data 3 Register Address */
94 #define ADDR_TAB_DATA3_REG_ADDR 0x14u
96 /* Address Table Data 4 PHY Address */
97 #define ADDR_TAB_DATA4_PHY_ADDR 0x15u
98 /* Address Table Data 4 Register Address */
99 #define ADDR_TAB_DATA4_REG_ADDR 0x15u
101 /* WoL Control Register PHY Address */
102 #define WOLL_CTRL_REG_PHY_ADDR 0x15u
103 /* WoL Control Register Register Address */
104 #define WOLL_CTRL_REG_REG_ADDR 0x1bu
106 /* PHY address 0x18h */
107 #define PHY_ADDRESS_18H 0x18u
109 /* Interrupt Status Register PHY Address. */
110 #define INT_STAT_PHY_ADDR 0x18u
111 /* Interrupt Status Register Register Address. */
112 #define INT_STAT_REG_ADDR 0x18u
114 /* Interrupt Mask & Control Register PHY Address. */
115 #define INT_MASK_CTRL_PHY_ADDR 0x18u
116 /* Interrupt Mask & Control Register Register Address. */
117 #define INT_MASK_CTRL_REG_ADDR 0x19u
119 #define PORT5_MAC_CONTROL 0x15u
121 #define P5_SPEED_100M ~BIT(0)
142 #define IRQ_LED_CONTROL 0x17u
143 /* LED mode 0:
145 * 100M link fail - LED off
146 * 100M link ok and no TX/RX activity - LED on
147 * 100M link ok and TX/RX activity - LED blinking
149 * No colision: - LED off
150 * Colision: - LED blinking
152 * 10M link fail - LED off
153 * 10M link ok and no TX/RX activity - LED on
154 * 10M link ok and TX/RX activity - LED blinking
156 #define LED_MODE_0 ~(BIT(0) | BIT(1))