231 	uint16_t tmp;  in enc424j600_init_filters()  local
240 		enc424j600_read_sfru(dev, ENC424J600_SFR1_ERXFCONL, &tmp);  in enc424j600_init_filters()
241 		LOG_DBG("ERXFCON: 0x%04x", tmp);  in enc424j600_init_filters()
247 	uint16_t tmp;  in enc424j600_init_phy()  local
257 		enc424j600_read_phy(dev, ENC424J600_PSFR_PHANA, &tmp);  in enc424j600_init_phy()
258 		LOG_DBG("PHANA: 0x%04x", tmp);  in enc424j600_init_phy()
261 	enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);  in enc424j600_init_phy()
262 	tmp |= ENC424J600_PHCON1_RENEG;  in enc424j600_init_phy()
263 	LOG_DBG("PHCON1: 0x%04x", tmp);  in enc424j600_init_phy()
264 	enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);  in enc424j600_init_phy()
269 	uint16_t tmp;  in enc424j600_setup_mac()  local
273 		enc424j600_read_phy(dev, ENC424J600_PSFR_PHANLPA, &tmp);  in enc424j600_setup_mac()
274 		LOG_DBG("PHANLPA: 0x%04x", tmp);  in enc424j600_setup_mac()
277 	enc424j600_read_phy(dev, ENC424J600_PSFR_PHSTAT3, &tmp);  in enc424j600_setup_mac()
279 	if (tmp & ENC424J600_PHSTAT3_SPDDPX_100) {  in enc424j600_setup_mac()
281 	} else if (tmp & ENC424J600_PHSTAT3_SPDDPX_10) {  in enc424j600_setup_mac()
287 	if (tmp & ENC424J600_PHSTAT3_SPDDPX_FD) {  in enc424j600_setup_mac()
300 		enc424j600_read_sfru(dev, ENC424J600_SFR2_MACON2L, &tmp);  in enc424j600_setup_mac()
301 		LOG_DBG("MACON2: 0x%04x", tmp);  in enc424j600_setup_mac()
303 		enc424j600_read_sfru(dev, ENC424J600_SFR2_MAMXFLL, &tmp);  in enc424j600_setup_mac()
304 		LOG_DBG("MAMXFL (maximum frame length): %u", tmp);  in enc424j600_setup_mac()
313 	uint16_t tmp;  in enc424j600_tx()  local
334 		enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);  in enc424j600_tx()
335 	} while (tmp & ENC424J600_ECON1_TXRTS);  in enc424j600_tx()
338 		enc424j600_read_sfru(dev, ENC424J600_SFR0_ETXSTATL, &tmp);  in enc424j600_tx()
339 		LOG_DBG("ETXSTAT: 0x%04x", tmp);  in enc424j600_tx()
356 	uint16_t tmp;  in enc424j600_rx()  local
363 		enc424j600_read_sfru(dev, ENC424J600_SFR4_ERXRDPTL, &tmp);  in enc424j600_rx()
364 		LOG_DBG("set ERXRDPT to 0x%04x", tmp);  in enc424j600_rx()
371 		enc424j600_read_sfru(dev, ENC424J600_SFR4_ERXRDPTL, &tmp);  in enc424j600_rx()
372 		LOG_DBG("ERXRDPT is 0x%04x now", tmp);  in enc424j600_rx()
432 		tmp = ENC424J600_RXEND - 1;  in enc424j600_rx()
435 		tmp = context->next_pkt_ptr - 2;  in enc424j600_rx()
438 	enc424j600_write_sfru(dev, ENC424J600_SFR0_ERXTAILL, tmp);  in enc424j600_rx()
508 	uint16_t tmp;  in enc424j600_get_config()  local
522 		enc424j600_read_phy(dev, ENC424J600_PSFR_PHSTAT3, &tmp);  in enc424j600_get_config()
524 		if (tmp & ENC424J600_PHSTAT3_SPDDPX_100) {  in enc424j600_get_config()
527 		} else if (tmp & ENC424J600_PHSTAT3_SPDDPX_10) {  in enc424j600_get_config()
536 		enc424j600_read_phy(dev, ENC424J600_PSFR_PHSTAT3, &tmp);  in enc424j600_get_config()
541 		if (tmp & ENC424J600_PHSTAT3_SPDDPX_FD) {  in enc424j600_get_config()
564 	uint16_t tmp;  in enc424j600_set_config()  local
576 		tmp = config->mac_address.addr[0] | config->mac_address.addr[1] << 8;  in enc424j600_set_config()
577 		enc424j600_write_sfru(dev, ENC424J600_SFR3_MAADR1L, tmp);  in enc424j600_set_config()
580 		tmp = config->mac_address.addr[2] | config->mac_address.addr[3] << 8;  in enc424j600_set_config()
581 		enc424j600_write_sfru(dev, ENC424J600_SFR3_MAADR2L, tmp);  in enc424j600_set_config()
584 		tmp = config->mac_address.addr[4] | config->mac_address.addr[5] << 8;  in enc424j600_set_config()
585 		enc424j600_write_sfru(dev, ENC424J600_SFR3_MAADR3L, tmp);  in enc424j600_set_config()
611 	uint16_t tmp;  in enc424j600_start_device()  local
624 	enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);  in enc424j600_start_device()
625 	tmp &= ~ENC424J600_PHCON1_PSLEEP;  in enc424j600_start_device()
626 	enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);  in enc424j600_start_device()
641 	uint16_t tmp;  in enc424j600_stop_device()  local
655 		enc424j600_read_sfru(dev, ENC424J600_SFRX_ESTATL, &tmp);  in enc424j600_stop_device()
656 	} while (tmp & ENC424J600_ESTAT_RXBUSY);  in enc424j600_stop_device()
660 		enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);  in enc424j600_stop_device()
661 	} while (tmp & ENC424J600_ECON1_TXRTS);  in enc424j600_stop_device()
663 	enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);  in enc424j600_stop_device()
664 	tmp |= ENC424J600_PHCON1_PSLEEP;  in enc424j600_stop_device()
665 	enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);  in enc424j600_stop_device()
693 	uint16_t tmp;  in enc424j600_init()  local
729 		enc424j600_read_sfru(dev, ENC424J600_SFRX_EUDASTL, &tmp);  in enc424j600_init()
731 	} while (tmp != 0x4AFE && retries);  in enc424j600_init()
733 	if (tmp != 0x4AFE) {  in enc424j600_init()
741 		enc424j600_read_sfru(dev, ENC424J600_SFRX_ESTATL, &tmp);  in enc424j600_init()
743 	} while (!(tmp & ENC424J600_ESTAT_CLKRDY)  && retries);  in enc424j600_init()
745 	if (!(tmp & ENC424J600_ESTAT_CLKRDY)) {  in enc424j600_init()
753 	enc424j600_read_sfru(dev, ENC424J600_SFRX_EUDASTL, &tmp);  in enc424j600_init()
754 	if (tmp) {  in enc424j600_init()
764 		enc424j600_read_sfru(dev, ENC424J600_SFR3_EIEL, &tmp);  in enc424j600_init()
765 		LOG_DBG("EIE: 0x%04x", tmp);  in enc424j600_init()
784 	enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR1L, &tmp);  in enc424j600_init()
785 	context->mac_address[0] = tmp;  in enc424j600_init()
786 	context->mac_address[1] = tmp >> 8;  in enc424j600_init()
788 	enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR2L, &tmp);  in enc424j600_init()
789 	context->mac_address[2] = tmp;  in enc424j600_init()
790 	context->mac_address[3] = tmp >> 8;  in enc424j600_init()
792 	enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR3L, &tmp);  in enc424j600_init()
793 	context->mac_address[4] = tmp;  in enc424j600_init()
794 	context->mac_address[5] = tmp >> 8;  in enc424j600_init()
802 		enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);  in enc424j600_init()
803 		LOG_DBG("ECON1: 0x%04x", tmp);  in enc424j600_init()