Lines Matching +full:wuc +full:- +full:base
4 * SPDX-License-Identifier: Apache-2.0
80 /* WUC control device structure */
82 /* WUC pin mask */
95 const struct espi_it8xxx2_wuc wuc; member
189 /* I/O Port Base Address (data/command ports) */
206 * Mapping range is 4K bytes and base address is adjustable.
242 #define H2RAM_WINDOW_SIZE(ram_size) ((find_msb_set((ram_size) / 16) - 1) & 0x7)
247 /* Internal RAM base address on eSPI I/O space */
257 const struct espi_it8xxx2_config *const config = dev->config; in smfi_it8xxx2_init()
259 (struct smfi_it8xxx2_regs *)config->base_smfi; in smfi_it8xxx2_init()
266 gctrl->GCTRL_H2ROFSR = in smfi_it8xxx2_init()
267 (gctrl->GCTRL_H2ROFSR & ~IT8XXX2_ESPI_H2RAM_OFFSET_MASK) | in smfi_it8xxx2_init()
273 /* Set host RAM window 0 base address */ in smfi_it8xxx2_init()
274 smfi_reg->SMFI_HRAMW0BA = in smfi_it8xxx2_init()
277 smfi_reg->SMFI_HRAMW0AAS = in smfi_it8xxx2_init()
280 smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW0E); in smfi_it8xxx2_init()
286 /* Set host RAM window 1 base address */ in smfi_it8xxx2_init()
287 smfi_reg->SMFI_HRAMW1BA = in smfi_it8xxx2_init()
289 /* Set host RAM window 1 size. (read-only) */ in smfi_it8xxx2_init()
290 smfi_reg->SMFI_HRAMW1AAS = in smfi_it8xxx2_init()
294 smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW1E); in smfi_it8xxx2_init()
304 const struct espi_it8xxx2_config *const config = dev->config; in ec2i_it8xxx2_wait_status_cleared()
305 struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i; in ec2i_it8xxx2_wait_status_cleared()
307 while (ec2i->IBCTL & mask) { in ec2i_it8xxx2_wait_status_cleared()
315 const struct espi_it8xxx2_config *const config = dev->config; in ec2i_it8xxx2_write_pnpcfg()
316 struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i; in ec2i_it8xxx2_write_pnpcfg()
318 /* bit0: EC to I-Bus access enabled. */ in ec2i_it8xxx2_write_pnpcfg()
319 ec2i->IBCTL |= EC2I_IBCTL_CSAE; in ec2i_it8xxx2_write_pnpcfg()
326 ec2i->IBMAE |= EC2I_IBMAE_CFGAE; in ec2i_it8xxx2_write_pnpcfg()
328 ec2i->IHIOA = sel; in ec2i_it8xxx2_write_pnpcfg()
330 ec2i->IHD = data; in ec2i_it8xxx2_write_pnpcfg()
334 ec2i->IBMAE &= ~EC2I_IBMAE_CFGAE; in ec2i_it8xxx2_write_pnpcfg()
335 /* Disable EC to I-Bus access. */ in ec2i_it8xxx2_write_pnpcfg()
336 ec2i->IBCTL &= ~EC2I_IBCTL_CSAE; in ec2i_it8xxx2_write_pnpcfg()
363 const struct espi_it8xxx2_config *const config = dev->config; in pnpcfg_it8xxx2_init()
364 struct ec2i_regs *const ec2i = (struct ec2i_regs *)config->base_ec2i; in pnpcfg_it8xxx2_init()
368 gctrl->GCTRL_BADRSEL = 0x1; in pnpcfg_it8xxx2_init()
370 ec2i->LSIOHA |= 0x3; in pnpcfg_it8xxx2_init()
391 const struct espi_it8xxx2_config *const config = dev->config; in kbc_it8xxx2_ibf_isr()
392 struct espi_it8xxx2_data *const data = dev->data; in kbc_it8xxx2_ibf_isr()
393 struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc; in kbc_it8xxx2_ibf_isr()
403 kbc_evt->evt = HOST_KBC_EVT_IBF; in kbc_it8xxx2_ibf_isr()
409 kbc_evt->type = !!(kbc_reg->KBHISR & KBC_KBHISR_A2_ADDR); in kbc_it8xxx2_ibf_isr()
411 kbc_evt->data = kbc_reg->KBHIDIR; in kbc_it8xxx2_ibf_isr()
413 espi_send_callbacks(&data->callbacks, dev, evt); in kbc_it8xxx2_ibf_isr()
418 const struct espi_it8xxx2_config *const config = dev->config; in kbc_it8xxx2_obe_isr()
419 struct espi_it8xxx2_data *const data = dev->data; in kbc_it8xxx2_obe_isr()
420 struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc; in kbc_it8xxx2_obe_isr()
430 kbc_reg->KBHICR &= ~KBC_KBHICR_OBECIE; in kbc_it8xxx2_obe_isr()
433 kbc_evt->evt = HOST_KBC_EVT_OBE; in kbc_it8xxx2_obe_isr()
434 kbc_evt->data = 0; in kbc_it8xxx2_obe_isr()
435 kbc_evt->type = 0; in kbc_it8xxx2_obe_isr()
436 espi_send_callbacks(&data->callbacks, dev, evt); in kbc_it8xxx2_obe_isr()
441 const struct espi_it8xxx2_config *const config = dev->config; in kbc_it8xxx2_init()
442 struct kbc_regs *const kbc_reg = (struct kbc_regs *)config->base_kbc; in kbc_it8xxx2_init()
445 kbc_reg->KBIRQR = 0; in kbc_it8xxx2_init()
454 kbc_reg->KBHICR |= in kbc_it8xxx2_init()
473 const struct espi_it8xxx2_config *const config = dev->config; in pmc1_it8xxx2_ibf_isr()
474 struct espi_it8xxx2_data *const data = dev->data; in pmc1_it8xxx2_ibf_isr()
475 struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; in pmc1_it8xxx2_ibf_isr()
489 acpi_evt->type = !!(pmc_reg->PM1STS & PMC_PM1STS_A2_ADDR); in pmc1_it8xxx2_ibf_isr()
491 pmc_reg->PM1STS |= PMC_PM1STS_GPF; in pmc1_it8xxx2_ibf_isr()
492 acpi_evt->data = pmc_reg->PM1DI; in pmc1_it8xxx2_ibf_isr()
494 espi_send_callbacks(&data->callbacks, dev, evt); in pmc1_it8xxx2_ibf_isr()
499 const struct espi_it8xxx2_config *const config = dev->config; in pmc1_it8xxx2_init()
500 struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; in pmc1_it8xxx2_init()
503 pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE; in pmc1_it8xxx2_init()
516 struct espi_it8xxx2_data *const data = dev->data; in port80_it8xxx2_isr()
525 evt.evt_data = gctrl->GCTRL_P80HDR | (gctrl->GCTRL_P81HDR << 8); in port80_it8xxx2_isr()
527 evt.evt_data = gctrl->GCTRL_P80HDR; in port80_it8xxx2_isr()
530 gctrl->GCTRL_P80H81HSR |= BIT(0); in port80_it8xxx2_isr()
532 espi_send_callbacks(&data->callbacks, dev, evt); in port80_it8xxx2_isr()
542 gctrl->GCTRL_SPCTRL1 |= in port80_it8xxx2_init()
545 gctrl->GCTRL_SPCTRL1 |= IT8XXX2_GCTRL_ACP80; in port80_it8xxx2_init()
557 const struct espi_it8xxx2_config *const config = dev->config; in pmc2_it8xxx2_ibf_isr()
558 struct espi_it8xxx2_data *const data = dev->data; in pmc2_it8xxx2_ibf_isr()
559 struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; in pmc2_it8xxx2_ibf_isr()
567 pmc_reg->PM2STS |= PMC_PM2STS_GPF; in pmc2_it8xxx2_ibf_isr()
568 evt.evt_data = pmc_reg->PM2DI; in pmc2_it8xxx2_ibf_isr()
570 espi_send_callbacks(&data->callbacks, dev, evt); in pmc2_it8xxx2_ibf_isr()
575 const struct espi_it8xxx2_config *const config = dev->config; in pmc2_it8xxx2_init()
576 struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; in pmc2_it8xxx2_init()
579 pmc_reg->MBXCTRL |= PMC_MBXCTRL_DINT; in pmc2_it8xxx2_init()
581 pmc_reg->PM2CTL |= PMC_PM2CTL_IBFIE; in pmc2_it8xxx2_init()
630 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_configure()
632 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_configure()
636 switch (cfg->max_freq) { in espi_it8xxx2_configure()
653 return -EINVAL; in espi_it8xxx2_configure()
655 slave_reg->GCAPCFG1 = in espi_it8xxx2_configure()
656 (slave_reg->GCAPCFG1 & ~IT8XXX2_ESPI_MAX_FREQ_MASK) | capcfg1; in espi_it8xxx2_configure()
673 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_channel_ready()
675 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_channel_ready()
680 sts = slave_reg->CH_PC_CAPCFG3 & IT8XXX2_ESPI_PC_READY_MASK; in espi_it8xxx2_channel_ready()
683 sts = slave_reg->CH_VW_CAPCFG3 & IT8XXX2_ESPI_VW_READY_MASK; in espi_it8xxx2_channel_ready()
686 sts = slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK; in espi_it8xxx2_channel_ready()
689 sts = slave_reg->CH_FLASH_CAPCFG3 & IT8XXX2_ESPI_FC_READY_MASK; in espi_it8xxx2_channel_ready()
701 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_send_vwire()
703 (struct espi_vw_regs *)config->base_espi_vw; in espi_it8xxx2_send_vwire()
709 return -EIO; in espi_it8xxx2_send_vwire()
713 vw_reg->VW_INDEX[vw_index] |= level_mask; in espi_it8xxx2_send_vwire()
715 vw_reg->VW_INDEX[vw_index] &= ~level_mask; in espi_it8xxx2_send_vwire()
718 vw_reg->VW_INDEX[vw_index] |= valid_mask; in espi_it8xxx2_send_vwire()
726 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_receive_vwire()
728 (struct espi_vw_regs *)config->base_espi_vw; in espi_it8xxx2_receive_vwire()
734 return -EIO; in espi_it8xxx2_receive_vwire()
738 if (vw_reg->VW_INDEX[vw_index] & valid_mask) { in espi_it8xxx2_receive_vwire()
739 *level = !!(vw_reg->VW_INDEX[vw_index] & level_mask); in espi_it8xxx2_receive_vwire()
745 *level = !!(vw_reg->VW_INDEX[vw_index] & level_mask); in espi_it8xxx2_receive_vwire()
776 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_manage_callback()
778 return espi_manage_callback(&data->callbacks, callback, set); in espi_it8xxx2_manage_callback()
785 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_read_lpc_request()
789 (struct kbc_regs *)config->base_kbc; in espi_it8xxx2_read_lpc_request()
797 *data = !!(kbc_reg->KBHISR & KBC_KBHISR_OBF); in espi_it8xxx2_read_lpc_request()
800 *data = !!(kbc_reg->KBHISR & KBC_KBHISR_IBF); in espi_it8xxx2_read_lpc_request()
803 *data = kbc_reg->KBHISR; in espi_it8xxx2_read_lpc_request()
806 return -EINVAL; in espi_it8xxx2_read_lpc_request()
810 (struct pmc_regs *)config->base_pmc; in espi_it8xxx2_read_lpc_request()
818 *data = !!(pmc_reg->PM1STS & PMC_PM1STS_OBF); in espi_it8xxx2_read_lpc_request()
821 *data = !!(pmc_reg->PM1STS & PMC_PM1STS_IBF); in espi_it8xxx2_read_lpc_request()
824 *data = pmc_reg->PM1STS; in espi_it8xxx2_read_lpc_request()
833 return -EINVAL; in espi_it8xxx2_read_lpc_request()
848 return -EINVAL; in espi_it8xxx2_read_lpc_request()
853 return -ENOTSUP; in espi_it8xxx2_read_lpc_request()
863 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_write_lpc_request()
867 (struct kbc_regs *)config->base_kbc; in espi_it8xxx2_write_lpc_request()
871 kbc_reg->KBHIKDOR = (*data & 0xff); in espi_it8xxx2_write_lpc_request()
876 kbc_reg->KBHICR |= KBC_KBHICR_OBECIE; in espi_it8xxx2_write_lpc_request()
879 kbc_reg->KBHIMDOR = (*data & 0xff); in espi_it8xxx2_write_lpc_request()
884 kbc_reg->KBHICR |= KBC_KBHICR_OBECIE; in espi_it8xxx2_write_lpc_request()
907 kbc_reg->KBHICR |= KBC_KBHICR_IBFOBFCME; in espi_it8xxx2_write_lpc_request()
908 kbc_reg->KBHICR |= KBC_KBHICR_COBF; in espi_it8xxx2_write_lpc_request()
909 kbc_reg->KBHICR &= ~KBC_KBHICR_COBF; in espi_it8xxx2_write_lpc_request()
911 kbc_reg->KBHICR &= ~KBC_KBHICR_IBFOBFCME; in espi_it8xxx2_write_lpc_request()
917 _kbhicr = kbc_reg->KBHICR; in espi_it8xxx2_write_lpc_request()
921 kbc_reg->KBHISR |= (*data & 0xff); in espi_it8xxx2_write_lpc_request()
924 kbc_reg->KBHISR &= ~(*data & 0xff); in espi_it8xxx2_write_lpc_request()
927 return -EINVAL; in espi_it8xxx2_write_lpc_request()
931 (struct pmc_regs *)config->base_pmc; in espi_it8xxx2_write_lpc_request()
935 pmc_reg->PM1DO = (*data & 0xff); in espi_it8xxx2_write_lpc_request()
938 pmc_reg->PM1STS = (*data & 0xff); in espi_it8xxx2_write_lpc_request()
941 return -EINVAL; in espi_it8xxx2_write_lpc_request()
947 (struct pmc_regs *)config->base_pmc; in espi_it8xxx2_write_lpc_request()
960 pmc_reg->PM2DO = (*data & 0xff); in espi_it8xxx2_write_lpc_request()
962 pmc_reg->PM2STS &= ~PMC_PM2STS_GPF; in espi_it8xxx2_write_lpc_request()
965 return -EINVAL; in espi_it8xxx2_write_lpc_request()
970 return -ENOTSUP; in espi_it8xxx2_write_lpc_request()
993 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_send_oob()
995 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_send_oob()
997 (struct espi_queue1_regs *)config->base_espi_queue1; in espi_it8xxx2_send_oob()
999 (struct espi_oob_msg_packet *)pckt->buf; in espi_it8xxx2_send_oob()
1001 if (!(slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK)) { in espi_it8xxx2_send_oob()
1003 return -EIO; in espi_it8xxx2_send_oob()
1006 if (slave_reg->ESUCTRL0 & IT8XXX2_ESPI_UPSTREAM_BUSY) { in espi_it8xxx2_send_oob()
1008 return -EIO; in espi_it8xxx2_send_oob()
1011 if (pckt->len > ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE) { in espi_it8xxx2_send_oob()
1013 return -EINVAL; in espi_it8xxx2_send_oob()
1017 slave_reg->ESUCTRL1 = IT8XXX2_ESPI_CYCLE_TYPE_OOB; in espi_it8xxx2_send_oob()
1019 slave_reg->ESUCTRL2 = ESPI_TAG_LEN_FIELD(0, pckt->len); in espi_it8xxx2_send_oob()
1021 slave_reg->ESUCTRL3 = pckt->len & 0xff; in espi_it8xxx2_send_oob()
1024 for (int i = 0; i < pckt->len; i++) { in espi_it8xxx2_send_oob()
1025 queue1_reg->UPSTREAM_DATA[i] = oob_pckt->data_byte[i]; in espi_it8xxx2_send_oob()
1029 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE; in espi_it8xxx2_send_oob()
1031 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO; in espi_it8xxx2_send_oob()
1039 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_receive_oob()
1041 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_receive_oob()
1043 (struct espi_queue0_regs *)config->base_espi_queue0; in espi_it8xxx2_receive_oob()
1045 (struct espi_oob_msg_packet *)pckt->buf; in espi_it8xxx2_receive_oob()
1048 if (!(slave_reg->CH_OOB_CAPCFG3 & IT8XXX2_ESPI_OOB_READY_MASK)) { in espi_it8xxx2_receive_oob()
1050 return -EIO; in espi_it8xxx2_receive_oob()
1054 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_receive_oob()
1058 ret = k_sem_take(&data->oob_upstream_go, K_MSEC(ESPI_OOB_TIMEOUT_MS)); in espi_it8xxx2_receive_oob()
1059 if (ret == -EAGAIN) { in espi_it8xxx2_receive_oob()
1061 return -ETIMEDOUT; in espi_it8xxx2_receive_oob()
1066 oob_len = (slave_reg->ESOCTRL4 & IT8XXX2_ESPI_PUT_OOB_LEN_MASK); in espi_it8xxx2_receive_oob()
1071 if (oob_len > pckt->len) { in espi_it8xxx2_receive_oob()
1073 oob_len, pckt->len); in espi_it8xxx2_receive_oob()
1074 return -EINVAL; in espi_it8xxx2_receive_oob()
1077 pckt->len = oob_len; in espi_it8xxx2_receive_oob()
1080 oob_pckt->data_byte[i] = queue0_reg->PUT_OOB_DATA[i]; in espi_it8xxx2_receive_oob()
1088 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_oob_init()
1090 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_oob_init()
1093 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_oob_init()
1095 k_sem_init(&data->oob_upstream_go, 0, 1); in espi_it8xxx2_oob_init()
1099 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_INTERRUPT_ENABLE; in espi_it8xxx2_oob_init()
1102 slave_reg->ESOCTRL1 |= IT8XXX2_ESPI_PUT_OOB_INTERRUPT_ENABLE; in espi_it8xxx2_oob_init()
1127 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_trans()
1129 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_trans()
1131 (struct espi_queue1_regs *)config->base_espi_queue1; in espi_it8xxx2_flash_trans()
1133 if (!(slave_reg->CH_FLASH_CAPCFG3 & IT8XXX2_ESPI_FC_READY_MASK)) { in espi_it8xxx2_flash_trans()
1136 return -EIO; in espi_it8xxx2_flash_trans()
1139 if (slave_reg->ESUCTRL0 & IT8XXX2_ESPI_UPSTREAM_BUSY) { in espi_it8xxx2_flash_trans()
1141 return -EIO; in espi_it8xxx2_flash_trans()
1144 if (pckt->len > IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE) { in espi_it8xxx2_flash_trans()
1146 return -EINVAL; in espi_it8xxx2_flash_trans()
1150 slave_reg->ESUCTRL1 = tran; in espi_it8xxx2_flash_trans()
1152 slave_reg->ESUCTRL2 = (ESPI_FLASH_TAG << 4); in espi_it8xxx2_flash_trans()
1162 slave_reg->ESUCTRL3 = pckt->len; in espi_it8xxx2_flash_trans()
1164 queue1_reg->UPSTREAM_DATA[0] = (pckt->flash_addr >> 24) & 0xff; in espi_it8xxx2_flash_trans()
1165 queue1_reg->UPSTREAM_DATA[1] = (pckt->flash_addr >> 16) & 0xff; in espi_it8xxx2_flash_trans()
1166 queue1_reg->UPSTREAM_DATA[2] = (pckt->flash_addr >> 8) & 0xff; in espi_it8xxx2_flash_trans()
1167 queue1_reg->UPSTREAM_DATA[3] = pckt->flash_addr & 0xff; in espi_it8xxx2_flash_trans()
1175 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_read()
1176 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_flash_read()
1178 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_read()
1188 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE; in espi_it8xxx2_flash_read()
1190 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO; in espi_it8xxx2_flash_read()
1193 ret = k_sem_take(&data->flash_upstream_go, in espi_it8xxx2_flash_read()
1195 if (ret == -EAGAIN) { in espi_it8xxx2_flash_read()
1197 return -ETIMEDOUT; in espi_it8xxx2_flash_read()
1200 if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWD) { in espi_it8xxx2_flash_read()
1202 return -EIO; in espi_it8xxx2_flash_read()
1205 memcpy(pckt->buf, data->flash_buf, pckt->len); in espi_it8xxx2_flash_read()
1208 data->put_flash_len); in espi_it8xxx2_flash_read()
1216 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_write()
1217 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_flash_write()
1219 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_write()
1221 (struct espi_queue1_regs *)config->base_espi_queue1; in espi_it8xxx2_flash_write()
1231 for (int i = 0; i < pckt->len; i++) { in espi_it8xxx2_flash_write()
1232 queue1_reg->UPSTREAM_DATA[4 + i] = pckt->buf[i]; in espi_it8xxx2_flash_write()
1236 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE; in espi_it8xxx2_flash_write()
1238 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO; in espi_it8xxx2_flash_write()
1241 ret = k_sem_take(&data->flash_upstream_go, in espi_it8xxx2_flash_write()
1243 if (ret == -EAGAIN) { in espi_it8xxx2_flash_write()
1245 return -ETIMEDOUT; in espi_it8xxx2_flash_write()
1248 if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWOD) { in espi_it8xxx2_flash_write()
1250 return -EIO; in espi_it8xxx2_flash_write()
1259 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_erase()
1260 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_flash_erase()
1262 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_erase()
1272 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_ENABLE; in espi_it8xxx2_flash_erase()
1274 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_GO; in espi_it8xxx2_flash_erase()
1277 ret = k_sem_take(&data->flash_upstream_go, in espi_it8xxx2_flash_erase()
1279 if (ret == -EAGAIN) { in espi_it8xxx2_flash_erase()
1281 return -ETIMEDOUT; in espi_it8xxx2_flash_erase()
1284 if (data->put_flash_cycle_type != ESPI_IT8XXX2_PUT_FLASH_C_SCWOD) { in espi_it8xxx2_flash_erase()
1286 return -EIO; in espi_it8xxx2_flash_erase()
1294 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_upstream_done_isr()
1295 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_flash_upstream_done_isr()
1297 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_upstream_done_isr()
1299 (struct espi_queue1_regs *)config->base_espi_queue1; in espi_it8xxx2_flash_upstream_done_isr()
1301 data->put_flash_cycle_type = slave_reg->ESUCTRL6; in espi_it8xxx2_flash_upstream_done_isr()
1302 data->put_flash_tag = slave_reg->ESUCTRL7 & in espi_it8xxx2_flash_upstream_done_isr()
1304 data->put_flash_len = slave_reg->ESUCTRL8 & in espi_it8xxx2_flash_upstream_done_isr()
1307 if (slave_reg->ESUCTRL1 == IT8XXX2_ESPI_CYCLE_TYPE_FLASH_READ) { in espi_it8xxx2_flash_upstream_done_isr()
1308 if (data->put_flash_len > IT8XXX2_ESPI_FLASH_MAX_PAYLOAD_SIZE) { in espi_it8xxx2_flash_upstream_done_isr()
1310 data->put_flash_len); in espi_it8xxx2_flash_upstream_done_isr()
1312 for (int i = 0; i < data->put_flash_len; i++) { in espi_it8xxx2_flash_upstream_done_isr()
1313 data->flash_buf[i] = in espi_it8xxx2_flash_upstream_done_isr()
1314 queue1_reg->UPSTREAM_DATA[i]; in espi_it8xxx2_flash_upstream_done_isr()
1319 k_sem_give(&data->flash_upstream_go); in espi_it8xxx2_flash_upstream_done_isr()
1324 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_flash_init()
1325 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_flash_init()
1327 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_flash_init()
1329 k_sem_init(&data->flash_upstream_go, 0, 1); in espi_it8xxx2_flash_init()
1332 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_INTERRUPT_ENABLE; in espi_it8xxx2_flash_init()
1361 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_vw_notify_system_state()
1369 espi_send_callbacks(&data->callbacks, dev, evt); in espi_it8xxx2_vw_notify_system_state()
1567 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_reset_vwidx_cache()
1569 (struct espi_vw_regs *)config->base_espi_vw; in espi_it8xxx2_reset_vwidx_cache()
1574 vw_reg->VW_INDEX[vwidx_isr_list[i].vw_index]; in espi_it8xxx2_reset_vwidx_cache()
1580 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_vw_isr()
1582 (struct espi_vw_regs *)config->base_espi_vw; in espi_it8xxx2_vw_isr()
1583 uint8_t vwidx_updated = vw_reg->VWCTRL1; in espi_it8xxx2_vw_isr()
1585 /* write-1 to clear */ in espi_it8xxx2_vw_isr()
1586 vw_reg->VWCTRL1 = vwidx_updated; in espi_it8xxx2_vw_isr()
1592 vw_flag = vw_reg->VW_INDEX[vwidx_isr_list[i].vw_index]; in espi_it8xxx2_vw_isr()
1603 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_ch_notify_system_state()
1610 espi_send_callbacks(&data->callbacks, dev, evt); in espi_it8xxx2_ch_notify_system_state()
1615 * A 0-to-1 or 1-to-0 transition on "Peripheral Channel Enable" bit.
1626 * A 0-to-1 or 1-to-0 transition on "Virtual Wire Channel Enable" bit.
1635 * A 0-to-1 or 1-to-0 transition on "OOB Message Channel Enable" bit.
1644 * A 0-to-1 or 1-to-0 transition on "Flash Access Channel Enable" bit.
1659 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_put_pc_status_isr()
1661 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_put_pc_status_isr()
1664 * TODO: To check cycle type (bit[3-0] at ESPCTRL0) and make in espi_it8xxx2_put_pc_status_isr()
1669 /* write-1-clear to release PC_FREE */ in espi_it8xxx2_put_pc_status_isr()
1670 slave_reg->ESPCTRL0 = IT8XXX2_ESPI_INTERRUPT_PUT_PC; in espi_it8xxx2_put_pc_status_isr()
1676 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_upstream_channel_disable_isr()
1678 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_upstream_channel_disable_isr()
1682 /* write-1 to clear this bit */ in espi_it8xxx2_upstream_channel_disable_isr()
1683 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_CHANNEL_DISABLE; in espi_it8xxx2_upstream_channel_disable_isr()
1688 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_put_oob_status_isr()
1689 struct espi_it8xxx2_data *const data = dev->data; in espi_it8xxx2_put_oob_status_isr()
1691 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_put_oob_status_isr()
1698 /* Write-1 to clear this bit for the next coming posted transaction. */ in espi_it8xxx2_put_oob_status_isr()
1699 slave_reg->ESOCTRL0 |= IT8XXX2_ESPI_PUT_OOB_STATUS; in espi_it8xxx2_put_oob_status_isr()
1702 k_sem_give(&data->oob_upstream_go); in espi_it8xxx2_put_oob_status_isr()
1705 evt.evt_details = (slave_reg->ESOCTRL4 & IT8XXX2_ESPI_PUT_OOB_LEN_MASK); in espi_it8xxx2_put_oob_status_isr()
1706 espi_send_callbacks(&data->callbacks, dev, evt); in espi_it8xxx2_put_oob_status_isr()
1714 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_upstream_done_isr()
1716 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_upstream_done_isr()
1720 if (slave_reg->ESUCTRL1 != IT8XXX2_ESPI_CYCLE_TYPE_OOB) { in espi_it8xxx2_upstream_done_isr()
1725 /* write-1 to clear this bit */ in espi_it8xxx2_upstream_done_isr()
1726 slave_reg->ESUCTRL0 |= IT8XXX2_ESPI_UPSTREAM_DONE; in espi_it8xxx2_upstream_done_isr()
1728 slave_reg->ESUCTRL0 &= ~IT8XXX2_ESPI_UPSTREAM_ENABLE; in espi_it8xxx2_upstream_done_isr()
1749 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_isr()
1751 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_isr()
1753 uint8_t espi_event = slave_reg->ESGCTRL0; in espi_it8xxx2_isr()
1755 uint8_t espi_upstream = slave_reg->ESUCTRL0; in espi_it8xxx2_isr()
1758 /* write-1 to clear */ in espi_it8xxx2_isr()
1759 slave_reg->ESGCTRL0 = espi_event; in espi_it8xxx2_isr()
1774 if (slave_reg->ESPCTRL0 & IT8XXX2_ESPI_INTERRUPT_PUT_PC) { in espi_it8xxx2_isr()
1788 if (slave_reg->ESOCTRL0 & IT8XXX2_ESPI_PUT_OOB_STATUS) { in espi_it8xxx2_isr()
1804 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_enable_pad_ctrl()
1806 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_enable_pad_ctrl()
1810 slave_reg->ESGCTRL2 &= ~IT8XXX2_ESPI_INPUT_PAD_GATING; in espi_it8xxx2_enable_pad_ctrl()
1813 slave_reg->ESGCTRL2 |= IT8XXX2_ESPI_INPUT_PAD_GATING; in espi_it8xxx2_enable_pad_ctrl()
1819 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_enable_trans_irq()
1826 it8xxx2_wuc_clear_status(config->wuc.wucs, config->wuc.mask); in espi_it8xxx2_enable_trans_irq()
1842 struct espi_it8xxx2_data *const data = ESPI_IT8XXX2_SOC_DEV->data; in espi_it8xxx2_espi_reset_isr()
1844 bool espi_reset = gpio_pin_get(port, (find_msb_set(pins) - 1)); in espi_it8xxx2_espi_reset_isr()
1852 espi_send_callbacks(&data->callbacks, ESPI_IT8XXX2_SOC_DEV, evt); in espi_it8xxx2_espi_reset_isr()
1866 gpio_regs->GPIO_GCR = in espi_it8xxx2_enable_reset()
1867 (gpio_regs->GPIO_GCR & ~IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK) | in espi_it8xxx2_enable_reset()
1888 .wuc = IT8XXX2_DT_WUC_ITEMS_FUNC(0, 0),
1898 const struct espi_it8xxx2_config *const config = dev->config; in espi_it8xxx2_init()
1900 (struct espi_vw_regs *)config->base_espi_vw; in espi_it8xxx2_init()
1902 (struct espi_slave_regs *)config->base_espi_slave; in espi_it8xxx2_init()
1906 gctrl->GCTRL_RSTS = (gctrl->GCTRL_RSTS & in espi_it8xxx2_init()
1938 vw_reg->VWCTRL0 |= IT8XXX2_ESPI_VW_INTERRUPT_ENABLE; in espi_it8xxx2_init()
1944 vw_reg->VWCTRL2 |= IT8XXX2_ESPI_VW_RESET_PLTRST; in espi_it8xxx2_init()
1955 slave_reg->ESGCTRL1 |= IT8XXX2_ESPI_INTERRUPT_ENABLE; in espi_it8xxx2_init()
1964 * Enable eSPI to WUC. in espi_it8xxx2_init()
1967 slave_reg->ESGCTRL2 |= IT8XXX2_ESPI_TO_WUC_ENABLE; in espi_it8xxx2_init()
1970 it8xxx2_wuc_clear_status(config->wuc.wucs, config->wuc.mask); in espi_it8xxx2_init()
1971 it8xxx2_wuc_enable(config->wuc.wucs, config->wuc.mask); in espi_it8xxx2_init()