Lines Matching full:pd
236 static int init_rm(struct dma_iproc_pax_data *pd) in init_rm() argument
240 k_mutex_lock(&pd->dma_lock, K_FOREVER); in init_rm()
244 if ((sys_read32(RM_COMM_REG(pd, RM_COMM_MAIN_HW_INIT_DONE)) & in init_rm()
251 k_mutex_unlock(&pd->dma_lock); in init_rm()
262 static void rm_cfg_start(struct dma_iproc_pax_data *pd) in rm_cfg_start() argument
266 k_mutex_lock(&pd->dma_lock, K_FOREVER); in rm_cfg_start()
269 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
271 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
275 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
279 RM_COMM_REG(pd, RM_COMM_MSI_DISABLE)); in rm_cfg_start()
281 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
283 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
286 sys_write32(RM_COMM_AE_TIMEOUT_VAL, RM_COMM_REG(pd, in rm_cfg_start()
288 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
290 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
293 val = sys_read32(RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
295 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
297 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
300 val = sys_read32(RM_COMM_REG(pd, RM_COMM_AXI_CONTROL)); in rm_cfg_start()
302 sys_write32(val, RM_COMM_REG(pd, RM_COMM_AXI_CONTROL)); in rm_cfg_start()
306 RM_COMM_REG(pd, RM_COMM_TIMER_CONTROL_0)); in rm_cfg_start()
308 RM_COMM_REG(pd, RM_COMM_TIMER_CONTROL_1)); in rm_cfg_start()
310 RM_COMM_REG(pd, RM_COMM_RM_BURST_LENGTH)); in rm_cfg_start()
313 val = sys_read32(RM_COMM_REG(pd, RM_COMM_MASK_SEQUENCE_MAX_COUNT)); in rm_cfg_start()
315 sys_write32(val, RM_COMM_REG(pd, RM_COMM_MASK_SEQUENCE_MAX_COUNT)); in rm_cfg_start()
317 k_mutex_unlock(&pd->dma_lock); in rm_cfg_start()
320 static void rm_ring_clear_stats(struct dma_iproc_pax_data *pd, in rm_ring_clear_stats() argument
324 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_RECV_LS)); in rm_ring_clear_stats()
325 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_RECV_MS)); in rm_ring_clear_stats()
326 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_TRANS_LS)); in rm_ring_clear_stats()
327 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_TRANS_MS)); in rm_ring_clear_stats()
328 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_OUTSTAND)); in rm_ring_clear_stats()
331 static void rm_cfg_finish(struct dma_iproc_pax_data *pd) in rm_cfg_finish() argument
335 k_mutex_lock(&pd->dma_lock, K_FOREVER); in rm_cfg_finish()
338 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_finish()
340 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_finish()
342 k_mutex_unlock(&pd->dma_lock); in rm_cfg_finish()
346 static inline void set_ring_active(struct dma_iproc_pax_data *pd, in set_ring_active() argument
352 val = sys_read32(RM_RING_REG(pd, idx, RING_CONTROL)); in set_ring_active()
358 sys_write32(val, RM_RING_REG(pd, idx, RING_CONTROL)); in set_ring_active()
361 static int init_ring(struct dma_iproc_pax_data *pd, enum ring_idx idx) in init_ring() argument
364 uintptr_t desc = (uintptr_t)pd->ring[idx].bd; in init_ring()
365 uintptr_t cmpl = (uintptr_t)pd->ring[idx].cmpl; in init_ring()
368 k_mutex_lock(&pd->dma_lock, K_FOREVER); in init_ring()
371 sys_read32(RM_RING_REG(pd, idx, RING_CMPL_WRITE_PTR)); in init_ring()
374 sys_write32(0x0, RM_RING_REG(pd, idx, RING_CONTROL)); in init_ring()
377 sys_write32(RING_CONTROL_FLUSH, RM_RING_REG(pd, idx, RING_CONTROL)); in init_ring()
379 if (sys_read32(RM_RING_REG(pd, idx, RING_FLUSH_DONE)) & in init_ring()
393 sys_write32(0x0, RM_RING_REG(pd, idx, RING_CONTROL)); in init_ring()
396 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CTRL_REG(idx))); in init_ring()
398 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CTRL_REG(idx))); in init_ring()
405 sys_write32(val, RM_RING_REG(pd, idx, RING_CMPL_WR_PTR_DDR_CONTROL)); in init_ring()
408 sys_write32(val, RM_RING_REG(pd, idx, RING_BD_START_ADDR)); in init_ring()
410 sys_write32(val, RM_RING_REG(pd, idx, RING_CMPL_START_ADDR)); in init_ring()
411 val = sys_read32(RM_RING_REG(pd, idx, RING_BD_READ_PTR)); in init_ring()
414 set_ring_active(pd, idx, false); in init_ring()
415 rm_ring_clear_stats(pd, idx); in init_ring()
417 k_mutex_unlock(&pd->dma_lock); in init_ring()
469 struct dma_iproc_pax_data *pd = dev->data; in process_cmpl_event() local
471 struct dma_iproc_pax_ring_data *ring = &(pd->ring[idx]); in process_cmpl_event()
478 wr_offs = sys_read32(RM_RING_REG(pd, idx, in process_cmpl_event()
501 is_outstanding = sys_read32(RM_RING_REG(pd, idx, in process_cmpl_event()
528 struct dma_iproc_pax_data *pd = dev->data; in peek_ring_cmpl() local
530 struct dma_iproc_pax_ring_data *ring = &(pd->ring[idx]); in peek_ring_cmpl()
537 wr_offs = sys_read32(RM_RING_REG(pd, idx, in peek_ring_cmpl()
559 struct dma_iproc_pax_data *pd = dev->data; in rm_isr() local
562 status = sys_read32(RM_COMM_REG(pd, RM_COMM_MSI_INTR_INTERRUPT_STATUS)); in rm_isr()
563 sys_write32(status, RM_COMM_REG(pd, in rm_isr()
567 err_stat = sys_read32(RM_COMM_REG(pd, in rm_isr()
570 RM_COMM_REG(pd, RM_COMM_DME_INTERRUPT_STATUS_CLEAR)); in rm_isr()
572 sys_read32(RM_COMM_REG(pd, in rm_isr()
575 RM_COMM_REG(pd, in rm_isr()
581 k_sem_give(&pd->ring[idx].alert); in rm_isr()
590 struct dma_iproc_pax_data *pd = dev->data; in dma_iproc_pax_init() local
599 pd->dma_base = cfg->dma_base; in dma_iproc_pax_init()
600 pd->rm_comm_base = cfg->rm_comm_base; in dma_iproc_pax_init()
601 pd->used_rings = (cfg->use_rings < PAX_DMA_RINGS_MAX) ? in dma_iproc_pax_init()
605 pd->dma_base, pd->rm_comm_base, pd->used_rings); in dma_iproc_pax_init()
608 k_mutex_init(&pd->dma_lock); in dma_iproc_pax_init()
611 if (init_rm(pd)) { in dma_iproc_pax_init()
616 rm_cfg_start(pd); in dma_iproc_pax_init()
619 for (r = 0; r < pd->used_rings; r++) { in dma_iproc_pax_init()
621 k_mutex_init(&pd->ring[r].lock); in dma_iproc_pax_init()
623 k_sem_init(&pd->ring[r].alert, 0, 1); in dma_iproc_pax_init()
625 pd->ring[r].idx = r; in dma_iproc_pax_init()
626 pd->ring[r].ring_base = cfg->rm_base + in dma_iproc_pax_init()
628 LOG_DBG("RING%d,VERSION:0x%x\n", pd->ring[r].idx, in dma_iproc_pax_init()
629 sys_read32(RM_RING_REG(pd, r, RING_VER))); in dma_iproc_pax_init()
632 pd->ring[r].ring_mem = (void *)((uintptr_t)cfg->bd_memory_base + in dma_iproc_pax_init()
635 if (!pd->ring[r].ring_mem) { in dma_iproc_pax_init()
640 mem_aligned = ((uintptr_t)pd->ring[r].ring_mem + in dma_iproc_pax_init()
644 pd->ring[r].cmpl = (void *)mem_aligned; in dma_iproc_pax_init()
645 pd->ring[r].bd = (void *)(mem_aligned + in dma_iproc_pax_init()
647 pd->ring[r].payload = (void *)((uintptr_t)pd->ring[r].bd + in dma_iproc_pax_init()
652 pd->ring[r].idx, in dma_iproc_pax_init()
653 pd->ring[r].ring_mem, in dma_iproc_pax_init()
656 pd->ring[r].idx, in dma_iproc_pax_init()
657 pd->ring[r].bd, in dma_iproc_pax_init()
658 pd->ring[r].cmpl, in dma_iproc_pax_init()
659 pd->ring[r].payload); in dma_iproc_pax_init()
662 prepare_ring(&(pd->ring[r])); in dma_iproc_pax_init()
665 init_ring(pd, r); in dma_iproc_pax_init()
669 rm_cfg_finish(pd); in dma_iproc_pax_init()
682 LOG_INF("%s RM setup %d rings\n", dev->name, pd->used_rings); in dma_iproc_pax_init()
707 struct dma_iproc_pax_data *pd = dev->data; in set_pkt_count() local
711 val = sys_read32(RM_RING_REG(pd, idx, in set_pkt_count()
715 sys_write32(val, RM_RING_REG(pd, idx, in set_pkt_count()
723 struct dma_iproc_pax_data *pd = dev->data; in wait_for_pkt_completion() local
726 ring = &(pd->ring[idx]); in wait_for_pkt_completion()
743 struct dma_iproc_pax_data *pd = dev->data; in dma_iproc_pax_do_xfer() local
752 ring = &(pd->ring[idx]); in dma_iproc_pax_do_xfer()
826 set_ring_active(pd, idx, true); in dma_iproc_pax_do_xfer()
841 set_ring_active(pd, idx, false); in dma_iproc_pax_do_xfer()
849 struct dma_iproc_pax_data *pd = dev->data; in dma_iproc_pax_configure() local
863 ring = &(pd->ring[channel]); in dma_iproc_pax_configure()
948 struct dma_iproc_pax_data *pd = dev->data; in dma_iproc_pax_transfer_start() local
955 ring = &(pd->ring[channel]); in dma_iproc_pax_transfer_start()