Lines Matching +full:0 +full:- +full:1
4 * SPDX-License-Identifier: Apache-2.0
18 #define ILITEK_ILI9806E_COLMOD_RGB565 0x50
19 #define ILITEK_ILI9806E_COLMOD_RGB888 0x70
38 /* Change to Page 1 CMD */
39 {.reg = 0xff, .cmd_len = 5, .cmd = {0xFF, 0x98, 0x06, 0x04, 0x01}},
41 {.reg = 0x08, .cmd_len = 1, .cmd = {0x10}},
42 /* DE = 1 Active */
43 {.reg = 0x21, .cmd_len = 1, .cmd = {0x01}},
45 {.reg = 0x30, .cmd_len = 1, .cmd = {0x01}},
47 {.reg = 0x31, .cmd_len = 1, .cmd = {0x00}},
49 {.reg = 0x40, .cmd_len = 1, .cmd = {0x14}},
50 /* avdd +5.2v,avee-5.2v */
51 {.reg = 0x41, .cmd_len = 1, .cmd = {0x33}},
52 /* VGL=DDVDL+VCL-VCIP,VGH=2DDVDH-DDVDL */
53 {.reg = 0x42, .cmd_len = 1, .cmd = {0x02}},
55 {.reg = 0x43, .cmd_len = 1, .cmd = {0x09}},
57 {.reg = 0x44, .cmd_len = 1, .cmd = {0x06}},
59 {.reg = 0x50, .cmd_len = 1, .cmd = {0x70}},
61 {.reg = 0x51, .cmd_len = 1, .cmd = {0x70}},
63 {.reg = 0x52, .cmd_len = 1, .cmd = {0x00}},
65 {.reg = 0x53, .cmd_len = 1, .cmd = {0x48}},
67 {.reg = 0x60, .cmd_len = 1, .cmd = {0x07}},
68 {.reg = 0x61, .cmd_len = 1, .cmd = {0x00}},
69 {.reg = 0x62, .cmd_len = 1, .cmd = {0x08}},
70 {.reg = 0x63, .cmd_len = 1, .cmd = {0x00}},
71 /* Positive Gamma Control 1 */
72 {.reg = 0xa0, .cmd_len = 1, .cmd = {0x00}},
74 {.reg = 0xa1, .cmd_len = 1, .cmd = {0x03}},
76 {.reg = 0xa2, .cmd_len = 1, .cmd = {0x09}},
78 {.reg = 0xa3, .cmd_len = 1, .cmd = {0x0d}},
80 {.reg = 0xa4, .cmd_len = 1, .cmd = {0x06}},
82 {.reg = 0xa5, .cmd_len = 1, .cmd = {0x16}},
84 {.reg = 0xa6, .cmd_len = 1, .cmd = {0x09}},
86 {.reg = 0xa7, .cmd_len = 1, .cmd = {0x08}},
88 {.reg = 0xa8, .cmd_len = 1, .cmd = {0x03}},
90 {.reg = 0xa9, .cmd_len = 1, .cmd = {0x07}},
92 {.reg = 0xaa, .cmd_len = 1, .cmd = {0x06}},
94 {.reg = 0xab, .cmd_len = 1, .cmd = {0x05}},
96 {.reg = 0xac, .cmd_len = 1, .cmd = {0x0d}},
98 {.reg = 0xad, .cmd_len = 1, .cmd = {0x2c}},
100 {.reg = 0xae, .cmd_len = 1, .cmd = {0x26}},
102 {.reg = 0xaf, .cmd_len = 1, .cmd = {0x00}},
103 /* Negative Gamma Correction 1 */
104 {.reg = 0xc0, .cmd_len = 1, .cmd = {0x00}},
106 {.reg = 0xc1, .cmd_len = 1, .cmd = {0x04}},
108 {.reg = 0xc2, .cmd_len = 1, .cmd = {0x0b}},
110 {.reg = 0xc3, .cmd_len = 1, .cmd = {0x0f}},
112 {.reg = 0xc4, .cmd_len = 1, .cmd = {0x09}},
114 {.reg = 0xc5, .cmd_len = 1, .cmd = {0x18}},
116 {.reg = 0xc6, .cmd_len = 1, .cmd = {0x07}},
118 {.reg = 0xc7, .cmd_len = 1, .cmd = {0x08}},
120 {.reg = 0xc8, .cmd_len = 1, .cmd = {0x05}},
122 {.reg = 0xc9, .cmd_len = 1, .cmd = {0x09}},
124 {.reg = 0xca, .cmd_len = 1, .cmd = {0x07}},
126 {.reg = 0xcb, .cmd_len = 1, .cmd = {0x05}},
128 {.reg = 0xcc, .cmd_len = 1, .cmd = {0x0c}},
130 {.reg = 0xcd, .cmd_len = 1, .cmd = {0x2d}},
132 {.reg = 0xce, .cmd_len = 1, .cmd = {0x28}},
134 {.reg = 0xcf, .cmd_len = 1, .cmd = {0x00}},
137 {.reg = 0xff, .cmd_len = 5, .cmd = {0xFF, 0x98, 0x06, 0x04, 0x06}},
138 /* GIP Control 1 */
139 {.reg = 0x00, .cmd_len = 1, .cmd = {0x21}},
140 {.reg = 0x01, .cmd_len = 1, .cmd = {0x09}},
141 {.reg = 0x02, .cmd_len = 1, .cmd = {0x00}},
142 {.reg = 0x03, .cmd_len = 1, .cmd = {0x00}},
143 {.reg = 0x04, .cmd_len = 1, .cmd = {0x01}},
144 {.reg = 0x05, .cmd_len = 1, .cmd = {0x01}},
145 {.reg = 0x06, .cmd_len = 1, .cmd = {0x80}},
146 {.reg = 0x07, .cmd_len = 1, .cmd = {0x05}},
147 {.reg = 0x08, .cmd_len = 1, .cmd = {0x02}},
148 {.reg = 0x09, .cmd_len = 1, .cmd = {0x80}},
149 {.reg = 0x0a, .cmd_len = 1, .cmd = {0x00}},
150 {.reg = 0x0b, .cmd_len = 1, .cmd = {0x00}},
151 {.reg = 0x0c, .cmd_len = 1, .cmd = {0x0a}},
152 {.reg = 0x0d, .cmd_len = 1, .cmd = {0x0a}},
153 {.reg = 0x0e, .cmd_len = 1, .cmd = {0x00}},
154 {.reg = 0x0f, .cmd_len = 1, .cmd = {0x00}},
155 {.reg = 0x10, .cmd_len = 1, .cmd = {0xe0}},
156 {.reg = 0x11, .cmd_len = 1, .cmd = {0xe4}},
157 {.reg = 0x12, .cmd_len = 1, .cmd = {0x04}},
158 {.reg = 0x13, .cmd_len = 1, .cmd = {0x00}},
159 {.reg = 0x14, .cmd_len = 1, .cmd = {0x00}},
160 {.reg = 0x15, .cmd_len = 1, .cmd = {0xc0}},
161 {.reg = 0x16, .cmd_len = 1, .cmd = {0x08}},
162 {.reg = 0x17, .cmd_len = 1, .cmd = {0x00}},
163 {.reg = 0x18, .cmd_len = 1, .cmd = {0x00}},
164 {.reg = 0x19, .cmd_len = 1, .cmd = {0x00}},
165 {.reg = 0x1a, .cmd_len = 1, .cmd = {0x00}},
166 {.reg = 0x1b, .cmd_len = 1, .cmd = {0x00}},
167 {.reg = 0x1c, .cmd_len = 1, .cmd = {0x00}},
168 {.reg = 0x1d, .cmd_len = 1, .cmd = {0x00}},
170 {.reg = 0x20, .cmd_len = 1, .cmd = {0x01}},
171 {.reg = 0x21, .cmd_len = 1, .cmd = {0x23}},
172 {.reg = 0x22, .cmd_len = 1, .cmd = {0x45}},
173 {.reg = 0x23, .cmd_len = 1, .cmd = {0x67}},
174 {.reg = 0x24, .cmd_len = 1, .cmd = {0x01}},
175 {.reg = 0x25, .cmd_len = 1, .cmd = {0x23}},
176 {.reg = 0x26, .cmd_len = 1, .cmd = {0x45}},
177 {.reg = 0x27, .cmd_len = 1, .cmd = {0x67}},
179 {.reg = 0x30, .cmd_len = 1, .cmd = {0x01}},
180 {.reg = 0x31, .cmd_len = 1, .cmd = {0x11}},
181 {.reg = 0x32, .cmd_len = 1, .cmd = {0x00}},
182 {.reg = 0x33, .cmd_len = 1, .cmd = {0xee}},
183 {.reg = 0x34, .cmd_len = 1, .cmd = {0xff}},
184 {.reg = 0x35, .cmd_len = 1, .cmd = {0xcb}},
185 {.reg = 0x36, .cmd_len = 1, .cmd = {0xda}},
186 {.reg = 0x37, .cmd_len = 1, .cmd = {0xad}},
187 {.reg = 0x38, .cmd_len = 1, .cmd = {0xbc}},
188 {.reg = 0x39, .cmd_len = 1, .cmd = {0x76}},
189 {.reg = 0x3a, .cmd_len = 1, .cmd = {0x67}},
190 {.reg = 0x3b, .cmd_len = 1, .cmd = {0x22}},
191 {.reg = 0x3c, .cmd_len = 1, .cmd = {0x22}},
192 {.reg = 0x3d, .cmd_len = 1, .cmd = {0x22}},
193 {.reg = 0x3e, .cmd_len = 1, .cmd = {0x22}},
194 {.reg = 0x3f, .cmd_len = 1, .cmd = {0x22}},
195 {.reg = 0x40, .cmd_len = 1, .cmd = {0x22}},
197 {.reg = 0x53, .cmd_len = 1, .cmd = {0x10}},
198 {.reg = 0x54, .cmd_len = 1, .cmd = {0x10}},
200 {.reg = 0xff, .cmd_len = 5, .cmd = {0xff, 0x98, 0x06, 0x04, 0x07}},
202 {.reg = 0x18, .cmd_len = 1, .cmd = {0x1d}},
203 {.reg = 0x26, .cmd_len = 1, .cmd = {0xb2}},
204 {.reg = 0x02, .cmd_len = 1, .cmd = {0x77}},
205 {.reg = 0xe1, .cmd_len = 1, .cmd = {0x79}},
206 {.reg = 0x17, .cmd_len = 1, .cmd = {0x22}},
207 /* Change to Page 0 CMD for Normal command */
208 {.reg = 0xff, .cmd_len = 5, .cmd = {0xff, 0x98, 0x06, 0x04, 0x00}}};
213 const struct ili9806e_config *cfg = dev->config; in ili9806e_write_reg()
215 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len); in ili9806e_write_reg()
216 if (ret < 0) { in ili9806e_write_reg()
217 LOG_ERR("Failed writing reg: 0x%x result: (%d)", reg, ret); in ili9806e_write_reg()
221 return 0; in ili9806e_write_reg()
226 return ili9806e_write_reg(dev, reg, &value, 1); in ili9806e_write_reg_val()
232 int ret = 0; in ili9806e_write_sequence()
235 for (int i = 0; i < nr_cmds && ret == 0; i++) { in ili9806e_write_sequence()
236 ret = ili9806e_write_reg(dev, cmd->reg, cmd->cmd, cmd->cmd_len); in ili9806e_write_sequence()
237 if (ret < 0) { in ili9806e_write_sequence()
238 LOG_ERR("Failed writing sequence: 0x%x result: (%d)", cmd->reg, ret); in ili9806e_write_sequence()
249 const struct ili9806e_config *cfg = dev->config; in ili9806e_config()
253 if (ret < 0) { in ili9806e_config()
260 ret = ili9806e_write_reg(dev, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); in ili9806e_config()
261 if (ret < 0) { in ili9806e_config()
270 cfg->pixel_format == PIXEL_FORMAT_RGB_565 in ili9806e_config()
273 if (ret < 0) { in ili9806e_config()
278 ret = ili9806e_write_reg(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); in ili9806e_config()
284 const struct ili9806e_config *cfg = dev->config; in ili9806e_blanking_on()
287 if (cfg->backlight.port != NULL) { in ili9806e_blanking_on()
288 ret = gpio_pin_set_dt(&cfg->backlight, 0); in ili9806e_blanking_on()
295 return ili9806e_write_reg(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); in ili9806e_blanking_on()
300 const struct ili9806e_config *cfg = dev->config; in ili9806e_blanking_off()
303 if (cfg->backlight.port != NULL) { in ili9806e_blanking_off()
304 ret = gpio_pin_set_dt(&cfg->backlight, 1); in ili9806e_blanking_off()
311 return ili9806e_write_reg(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); in ili9806e_blanking_off()
317 const struct ili9806e_config *cfg = dev->config; in ili9806e_get_capabilities()
319 memset(capabilities, 0, sizeof(struct display_capabilities)); in ili9806e_get_capabilities()
320 capabilities->x_resolution = cfg->width; in ili9806e_get_capabilities()
321 capabilities->y_resolution = cfg->height; in ili9806e_get_capabilities()
322 capabilities->supported_pixel_formats = cfg->pixel_format; in ili9806e_get_capabilities()
323 capabilities->current_pixel_format = cfg->pixel_format; in ili9806e_get_capabilities()
329 const struct ili9806e_config *config = dev->config; in ili9806e_pixel_format()
332 if (pixel_format == config->pixel_format) { in ili9806e_pixel_format()
333 return 0; in ili9806e_pixel_format()
336 return -ENOTSUP; in ili9806e_pixel_format()
348 const struct ili9806e_config *cfg = dev->config; in ili9806e_init()
352 if (cfg->reset.port) { in ili9806e_init()
353 if (!gpio_is_ready_dt(&cfg->reset)) { in ili9806e_init()
355 return -ENODEV; in ili9806e_init()
357 k_sleep(K_MSEC(1)); in ili9806e_init()
359 ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE); in ili9806e_init()
360 if (ret < 0) { in ili9806e_init()
365 ret = gpio_pin_set_dt(&cfg->reset, 0); in ili9806e_init()
366 if (ret < 0) { in ili9806e_init()
370 k_sleep(K_MSEC(1)); in ili9806e_init()
372 ret = gpio_pin_set_dt(&cfg->reset, 1); in ili9806e_init()
373 if (ret < 0) { in ili9806e_init()
380 /* attach to MIPI-DSI host */ in ili9806e_init()
381 if (cfg->pixel_format == PIXEL_FORMAT_RGB_565) { in ili9806e_init()
386 mdev.data_lanes = cfg->data_lanes; in ili9806e_init()
388 mdev.timings.hactive = cfg->width; in ili9806e_init()
392 mdev.timings.vactive = cfg->height; in ili9806e_init()
397 ret = mipi_dsi_attach(cfg->mipi_dsi, cfg->channel, &mdev); in ili9806e_init()
398 if (ret < 0) { in ili9806e_init()
399 LOG_ERR("Could not attach to MIPI-DSI host"); in ili9806e_init()
403 if (cfg->backlight.port != NULL) { in ili9806e_init()
404 ret = gpio_pin_configure_dt(&cfg->backlight, GPIO_OUTPUT_ACTIVE); in ili9806e_init()
405 if (ret < 0) { in ili9806e_init()
417 return 0; in ili9806e_init()
423 .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
424 .backlight = GPIO_DT_SPEC_INST_GET_OR(n, bl_gpios, {0}), \
425 .data_lanes = DT_INST_PROP_BY_IDX(n, data_lanes, 0), \