52 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||  in enabled_clock()
53 	    ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||  in enabled_clock()
54 	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||  in enabled_clock()
55 	    ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||  in enabled_clock()
56 	    ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||  in enabled_clock()
57 	    ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||  in enabled_clock()
58 	    ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) {  in enabled_clock()
139 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {  in get_pllsrc_frequency()
141 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {  in get_pllsrc_frequency()
153 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {  in get_pllsrc()
155 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {  in get_pllsrc()
182 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_get_subsys_rate()
188 		if (IS_ENABLED(STM32_AHB5_DIV)) {  in stm32_clock_control_get_subsys_rate()
262 		if (IS_ENABLED(STM32_HSE_DIV2)) {  in stm32_clock_control_get_subsys_rate()
367 	if (IS_ENABLED(STM32_HSE_ENABLED)) {  in stm32_clock_switch_to_hsi()
368 		if (IS_ENABLED(STM32_HSE_DIV2)) {  in stm32_clock_switch_to_hsi()
391 	if (IS_ENABLED(STM32_PLL_SRC_HSE)) {  in set_up_plls()
394 	} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {  in set_up_plls()
414 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {  in set_up_plls()
419 	if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {  in set_up_plls()
424 	if (IS_ENABLED(STM32_PLL_R_ENABLED)) {  in set_up_plls()
446 	if (IS_ENABLED(STM32_HSE_ENABLED)) {  in set_up_fixed_clock_sources()
447 		if (IS_ENABLED(STM32_HSE_DIV2)) {  in set_up_fixed_clock_sources()
458 	if (IS_ENABLED(STM32_HSI_ENABLED)) {  in set_up_fixed_clock_sources()
469 	if (IS_ENABLED(STM32_LSI_ENABLED)) {  in set_up_fixed_clock_sources()
485 	if (IS_ENABLED(STM32_LSE_ENABLED)) {  in set_up_fixed_clock_sources()
530 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL) &&  in stm32_clock_control_init()
551 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_init()
574 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_init()
579 		if (IS_ENABLED(STM32_AHB5_DIV)) {  in stm32_clock_control_init()
586 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_init()
594 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {  in stm32_clock_control_init()
599 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {  in stm32_clock_control_init()