619 	uint16_t bitset1 = 0;  in litex_clk_set_mulreg()  local
632 	bitset1 = (ht << HIGH_TIME_POS) |  in litex_clk_set_mulreg()
635 	ret = litex_clk_change_value(KEEP_IN_MUL_REG1, bitset1, CLKFBOUT_REG1);  in litex_clk_set_mulreg()
977 	uint16_t bitset1, bitset2;  in litex_clk_set_duty_cycle()  local
1000 	bitset1 = (*high_time << HIGH_TIME_POS) |  in litex_clk_set_duty_cycle()
1005 		*edge, *high_time, *low_time, bitset1, bitset2);  in litex_clk_set_duty_cycle()
1007 	ret = litex_clk_set_clock(clkout_nr, REG1_DUTY_MASK, bitset1,  in litex_clk_set_duty_cycle()
1182 	uint16_t bitset1, bitset2, reg2_mask;  in litex_clk_set_phase()  local
1198 	bitset1 = (*phase_mux << PHASE_MUX_POS);  in litex_clk_set_phase()
1201 	ret = litex_clk_set_clock(clkout_nr, REG1_PHASE_MASK, bitset1,  in litex_clk_set_phase()
1209 		*phase_mux, *delay_time, bitset1, bitset2);  in litex_clk_set_phase()
1402 	uint16_t bitset1, bitset2;  in litex_clk_write_rate()  local
1412 	bitset1 = (*high_time << HIGH_TIME_POS)	|  in litex_clk_write_rate()
1423 		*no_cnt, *edge, *high_time, *low_time, bitset1, bitset2);  in litex_clk_write_rate()
1425 	ret = litex_clk_set_clock(lcko->id, REG1_FREQ_MASK, bitset1,  in litex_clk_write_rate()