26 static struct litex_clk_clkout *clkouts;/* clkout array for whole driver */
52 			m.clkout[5].reg1 = CLKOUT5_REG1;  in litex_clk_regs_addr_init()
53 			m.clkout[5].reg2 = CLKOUT5_REG2;  in litex_clk_regs_addr_init()
55 			m.clkout[i].reg1 = addr;  in litex_clk_regs_addr_init()
57 			m.clkout[i].reg2 = addr;  in litex_clk_regs_addr_init()
353 /* Return dividers of given CLKOUT */
363 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg1, &div);  in litex_clk_get_clkout_divider()
367 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &frac);  in litex_clk_get_clkout_divider()
412 static void litex_clk_print_clkout_regs(uint8_t clkout, uint8_t reg1,  in litex_clk_print_clkout_regs()  argument
418 	sprintf(reg_name, "CLKOUT%u REG1", clkout);  in litex_clk_print_clkout_regs()
421 	sprintf(reg_name, "CLKOUT%u REG2", clkout);  in litex_clk_print_clkout_regs()
432 		litex_clk_print_clkout_regs(i, drp_addr.clkout[i].reg1,  in litex_clk_print_all_regs()
433 					       drp_addr.clkout[i].reg2);  in litex_clk_print_all_regs()
439 	LOG_DBG("CLKOUT%d DUMP:", lcko->id);  in litex_clk_print_params()
545  * Set register values for given CLKOUT
562 					     drp_addr.clkout[clkout_nr].reg2);  in litex_clk_set_clock()
569 					     drp_addr.clkout[clkout_nr].reg1);  in litex_clk_set_clock()
843 /* Returns accurate duty ratio of given clkout*/
855 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &clkout_reg2);  in litex_clk_get_duty_cycle()
872 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg1, &clkout_reg1);  in litex_clk_get_duty_cycle()
986 		LOG_DBG("CLKOUT%d: setting duty: %u/%u",  in litex_clk_set_duty_cycle()
990 			LOG_ERR("CLKOUT%d: cannot set %d%% duty cycle",  in litex_clk_set_duty_cycle()
995 		LOG_ERR("CLKOUT%d: cannot set duty cycle when fractional divider enabled",  in litex_clk_set_duty_cycle()
1013 	LOG_INF("CLKOUT%d: set duty: %d%%", lcko->id,  in litex_clk_set_duty_cycle()
1113 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg1, &r1);  in litex_clk_get_phase_data()
1117 	ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &r2);  in litex_clk_get_phase_data()
1189 	LOG_DBG("CLKOUT%d: setting phase: %u deg", lcko->id, degrees);  in litex_clk_set_phase()
1193 		LOG_ERR("CLKOUT%d: phase offset %d deg is too high",  in litex_clk_set_phase()
1207 	LOG_INF("CLKOUT%d: set phase: %d deg", lcko->id, lcko->config.phase);  in litex_clk_set_phase()
1285 			LOG_DBG("CLKOUT%d: freq:%u div:%u gdiv:%u gmul:%u",  in litex_clk_calc_clkout_params()
1453 			LOG_INF("CLKOUT%d: updated rate: %u to %u HZ",  in litex_clk_update_clkouts()
1466 	LOG_DBG("CLKOUT%d: setting rate: %lu", lcko->id, rate);  in litex_clk_set_rate()
1483 	LOG_INF("CLKOUT%d: set rate: %u HZ", lcko->id, lcko->config.freq);  in litex_clk_set_rate()
1497 /* Set default clock value from device tree for given clkout*/
1533  *			all clkout parameters
1711 		LOG_ERR("CLKOUT memory allocation failure!");  in litex_clk_dts_global_read()
1739 /* Enable module, set global divider, multiplier, default clkout parameters */