254 static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj,  in _configure_path_mux()  argument
262 	rslt = cyhal_clock_reserve(clock_obj, reserve_obj);  in _configure_path_mux()
265 		rslt = cyhal_clock_set_source(clock_obj, clock_source_obj);  in _configure_path_mux()
271 static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj,  in _configure_clk_hf()  argument
278 	rslt = cyhal_clock_reserve(clock_obj, reserve_obj);  in _configure_clk_hf()
281 		rslt = cyhal_clock_set_source(clock_obj, clock_source_obj);  in _configure_clk_hf()
285 		rslt = cyhal_clock_set_divider(clock_obj, clock_div);  in _configure_clk_hf()
289 		rslt = cyhal_clock_set_enabled(clock_obj, true, true);  in _configure_clk_hf()
295 static cy_rslt_t _configure_clk_frequency_and_enable(cyhal_clock_t *clock_obj,  in _configure_clk_frequency_and_enable()  argument
303 	rslt = cyhal_clock_reserve(clock_obj, reserve_obj);  in _configure_clk_frequency_and_enable()
306 		rslt = cyhal_clock_set_frequency(clock_obj, frequency, NULL);  in _configure_clk_frequency_and_enable()
310 		rslt = cyhal_clock_set_enabled(clock_obj, true, true);  in _configure_clk_frequency_and_enable()
386 	cyhal_clock_t *clock_obj = NULL;  in clock_control_infineon_cat1_init()  local
394 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj;  in clock_control_infineon_cat1_init()
395 	if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IMO)) {  in clock_control_infineon_cat1_init()
400 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj;  in clock_control_infineon_cat1_init()
401 	if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IHO)) {  in clock_control_infineon_cat1_init()
412 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj;  in clock_control_infineon_cat1_init()
415 	if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[0])) {  in clock_control_infineon_cat1_init()
422 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj;  in clock_control_infineon_cat1_init()
425 	if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[1])) {  in clock_control_infineon_cat1_init()
432 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj;  in clock_control_infineon_cat1_init()
435 	if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[2])) {  in clock_control_infineon_cat1_init()
442 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj;  in clock_control_infineon_cat1_init()
445 	if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[3])) {  in clock_control_infineon_cat1_init()
452 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj;  in clock_control_infineon_cat1_init()
455 	if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[4])) {  in clock_control_infineon_cat1_init()
462 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj;  in clock_control_infineon_cat1_init()
465 	rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,  in clock_control_infineon_cat1_init()
474 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj;  in clock_control_infineon_cat1_init()
477 	rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,  in clock_control_infineon_cat1_init()
487 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj;  in clock_control_infineon_cat1_init()
490 	rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,  in clock_control_infineon_cat1_init()
499 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj;  in clock_control_infineon_cat1_init()
503 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[0], clock_div)) {  in clock_control_infineon_cat1_init()
510 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj;  in clock_control_infineon_cat1_init()
514 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[1], clock_div)) {  in clock_control_infineon_cat1_init()
521 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj;  in clock_control_infineon_cat1_init()
525 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[2], clock_div)) {  in clock_control_infineon_cat1_init()
532 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj;  in clock_control_infineon_cat1_init()
536 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[3], clock_div)) {  in clock_control_infineon_cat1_init()
543 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj;  in clock_control_infineon_cat1_init()
547 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[4], clock_div)) {  in clock_control_infineon_cat1_init()
554 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj;  in clock_control_infineon_cat1_init()
558 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[5], clock_div)) {  in clock_control_infineon_cat1_init()
565 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj;  in clock_control_infineon_cat1_init()
569 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[6], clock_div)) {  in clock_control_infineon_cat1_init()
576 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj;  in clock_control_infineon_cat1_init()
580 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[7], clock_div)) {  in clock_control_infineon_cat1_init()
587 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj;  in clock_control_infineon_cat1_init()
591 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[8], clock_div)) {  in clock_control_infineon_cat1_init()
598 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj;  in clock_control_infineon_cat1_init()
602 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[9], clock_div)) {  in clock_control_infineon_cat1_init()
609 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj;  in clock_control_infineon_cat1_init()
613 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[10], clock_div)) {  in clock_control_infineon_cat1_init()
620 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj;  in clock_control_infineon_cat1_init()
624 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[11], clock_div)) {  in clock_control_infineon_cat1_init()
631 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj;  in clock_control_infineon_cat1_init()
635 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[12], clock_div)) {  in clock_control_infineon_cat1_init()
642 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj;  in clock_control_infineon_cat1_init()
646 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[13], clock_div)) {  in clock_control_infineon_cat1_init()
653 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj;  in clock_control_infineon_cat1_init()
656 	rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_FAST);  in clock_control_infineon_cat1_init()
658 		rslt = cyhal_clock_set_divider(clock_obj, clock_div);  in clock_control_infineon_cat1_init()
667 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj;  in clock_control_infineon_cat1_init()
670 	rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_PERI);  in clock_control_infineon_cat1_init()
672 		rslt = cyhal_clock_set_divider(clock_obj, clock_div);  in clock_control_infineon_cat1_init()
681 	clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj;  in clock_control_infineon_cat1_init()
684 	rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_SLOW);  in clock_control_infineon_cat1_init()
686 		rslt = cyhal_clock_set_divider(clock_obj, clock_div);  in clock_control_infineon_cat1_init()