3  * Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co., Ltd.
5  * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/esp32_clock.h>
22 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
28 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
33 #include <zephyr/dt-bindings/clock/esp32c2_clock.h>
37 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
41 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
507 		return -EALREADY;  in clock_control_esp32_on()
527 					uint32_t *rate)  in clock_control_esp32_get_rate()  argument
533 		*rate = esp_clk_tree_lp_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX);  in clock_control_esp32_get_rate()
536 		*rate = clk_hal_lp_slow_get_freq_hz();  in clock_control_esp32_get_rate()
539 		*rate = clk_hal_cpu_get_freq_hz();  in clock_control_esp32_get_rate()
596 					if (retry_32k_xtal-- > 0) {  in esp32_select_rtc_slow_clk()
600 					return -ENODEV;  in esp32_select_rtc_slow_clk()
637 	rtc_clk_cfg.xtal_freq = cpu_cfg->xtal_freq;  in esp32_cpu_clock_configure()
638 	rtc_clk_cfg.cpu_freq_mhz = cpu_cfg->cpu_freq;  in esp32_cpu_clock_configure()
654 	REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);  in esp32_cpu_clock_configure()
680 	/* On ESP32C6, MSPI source clock's default HS divider leads to 120MHz,  in esp32_cpu_clock_configure()
682 	 * SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider  in esp32_cpu_clock_configure()
694 	if (!ret || (new_config.source != cpu_cfg->clk_src)) {  in esp32_cpu_clock_configure()
696 		return -EINVAL;  in esp32_cpu_clock_configure()
701 	/* Re-calculate the ccount to make time calculation correct. */  in esp32_cpu_clock_configure()
720 					 void *data)  in clock_control_esp32_configure()  argument
722 	struct esp32_clock_config *new_cfg = data;  in clock_control_esp32_configure()
727 		rtc_clk_fast_src_set(new_cfg->rtc.rtc_fast_clock_src);  in clock_control_esp32_configure()
730 		ret = esp32_select_rtc_slow_clk(new_cfg->rtc.rtc_slow_clock_src);  in clock_control_esp32_configure()
734 		new_cfg->cpu.xtal_freq = new_cfg->cpu.xtal_freq > MHZ(1)  in clock_control_esp32_configure()
735 						 ? new_cfg->cpu.xtal_freq / MHZ(1)  in clock_control_esp32_configure()
736 						 : new_cfg->cpu.xtal_freq;  in clock_control_esp32_configure()
737 		new_cfg->cpu.cpu_freq = new_cfg->cpu.cpu_freq > MHZ(1)  in clock_control_esp32_configure()
738 						? new_cfg->cpu.cpu_freq / MHZ(1)  in clock_control_esp32_configure()
739 						: new_cfg->cpu.cpu_freq;  in clock_control_esp32_configure()
740 		ret = esp32_cpu_clock_configure(&new_cfg->cpu);  in clock_control_esp32_configure()
744 		return -EINVAL;  in clock_control_esp32_configure()
751 	const struct esp32_clock_config *cfg = dev->config;  in clock_control_esp32_init()
777 	ret = esp32_cpu_clock_configure(&cfg->cpu);  in clock_control_esp32_init()
785 	rtc_clk_fast_src_set(cfg->rtc.rtc_fast_clock_src);  in clock_control_esp32_init()
787 	ret = esp32_select_rtc_slow_clk(cfg->rtc.rtc_slow_clock_src);  in clock_control_esp32_init()