95 	for (uint8_t chan = 0; chan < drv_data->act_num_chan; chan++) {  in dmic_mcux_activate_channels()  local
97 		mask |= BIT(dmic_mcux_hw_chan(drv_data, chan));  in dmic_mcux_activate_channels()
115 	for (uint8_t chan = 0; chan < num_chan; chan++) {  in dmic_mcux_enable_dma()  local
117 		hw_chan = dmic_mcux_hw_chan(drv_data, chan);  in dmic_mcux_enable_dma()
153 	for (uint8_t chan = 0; chan < num_chan; chan++) {  in dmic_mcux_reload_dma()  local
155 		hw_chan = dmic_mcux_hw_chan(drv_data, chan);  in dmic_mcux_reload_dma()
158 		dst = (uint32_t)(((uint16_t *)buffer) + chan);  in dmic_mcux_reload_dma()
303 	for (uint8_t chan = 0; chan < num_chan; chan++) {  in dmic_mcux_setup_dma()  local
305 		hw_chan = dmic_mcux_hw_chan(drv_data, chan);  in dmic_mcux_setup_dma()
319 				(uint32_t)(((uint16_t *)dma_buf) + chan);  in dmic_mcux_setup_dma()
360 				  uint8_t chan, enum pdm_lr lr)  in dmic_mcux_init_channel()  argument
364 	if (!drv_data->pdm_channels[chan]) {  in dmic_mcux_init_channel()
369 	drv_data->pdm_channels[chan]->dmic_channel_cfg.osr = osr;  in dmic_mcux_init_channel()
371 	DMIC_ConfigChannel(drv_data->base_address, (dmic_channel_t)chan,  in dmic_mcux_init_channel()
373 			   &drv_data->pdm_channels[chan]->dmic_channel_cfg);  in dmic_mcux_init_channel()
377 	DMIC_FifoChannel(drv_data->base_address, chan, 15, true, true);  in dmic_mcux_init_channel()
379 	DMIC_EnableChannelInterrupt(drv_data->base_address, chan, false);  in dmic_mcux_init_channel()
488 	for (uint8_t chan = 0; chan < channel->req_num_chan; chan += 2) {  in dmic_mcux_configure()  local
492 				       chan, &hw_chan_0, &lr_0);  in dmic_mcux_configure()
493 		if ((chan + 1) < channel->req_num_chan) {  in dmic_mcux_configure()
497 					       chan + 1, &hw_chan_1, &lr_1);  in dmic_mcux_configure()
506 					     dmic_mcux_hw_chan(drv_data, chan),  in dmic_mcux_configure()
512 		if ((chan + 1) < channel->req_num_chan) {  in dmic_mcux_configure()
516 								       chan + 1),  in dmic_mcux_configure()