Lines Matching refs:to
8 HART modem which enables the bidirectional transfer of digital data over a current loop, to/from
24 - 44.1μA/MHz ACTIVE Mode at 0.9V up to 12MHzCoremark®
25 - 64.5μA/MHz ACTIVE Mode at 1.1V up to 100MHzCoremark
32 - 12 Channels, Assignable to Either ADC
37 - Up to Two I2C
38 - Up to Two UARTs
39 - Up to 23 GPIOs
40 - Up to Five 32-Bit Timers
47 - TRNG Compliant to SP800-90B
49 - Secure Bootloader to Protect IP/Firmware
50 - Wide, -40°C to +105°C Operating TemperatureRange
55 …- HART Compatible Secondary Master with the Ability to Connect to Existing 4-20mA Current Loop and…
56 - USB 2.0 Micro B to Serial UART
59 - Access to 4 Analog Inputs Through SMA Connectors Configured as Differential
60 - Access to 8 Analog Inputs Through 0.1in Headers Configured as Single-Ended
109 | | | | Closed | | | Connects red LED D1 to P1_9. …
116 | | | | Closed | | | Connects green LED D2 to P1_10. …
123 | | | | Closed | | | Connects 3V3 to I2C0_SCLK. …
128 | | | | Open | | | Disconnects 3V3 to I2C_SDA. …
130 | | | | Closed | | | Connects 3V3 to I2C_SDA. …
137 | | | | Closed | | | Connects UART0_RX (P0.8) to the SWD connector. …
144 | | | | Closed | | | Connects UART0_TX (P0.9) to the SWD connector. …
151 | | | | Closed | | | Connects REF0N to ground. …
158 | | | | Closed | | | Connects REF1N to ground. …
165 | | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.…
169 | | | HART_OUT | | | 3-4 | | | Connects RX of USB - serial bridge to HART_OUT (P0…
173 | | | HART_RTS | | | 4-5 | | | Connects TX of USB - serial bridge to HART_RTS (P1…
177 | | | HART_OCD | | | 7-8 | | | Connects TX of USB - serial bridge to HART_OCD (P0…
184 | | | | Closed | | | Connects boot load enable circuit to SWD_CLK (P0.1…
191 | | | | Closed | | | Connects FSK_IN to HART analog circuitry. …
198 | | | | Closed | | | Connects FSK_OUT to HART analog circuitry. …
205 | | | | Closed | | | Connects RCV_FSK to CC LOOP. …
212 | | | | Closed | | | Connects RCV_FSK to XFMR LOOP. …
219 | | | | Closed | | | Connects 249Ω resistor shunt to CC LOOP. …
239 | | | | Closed | | | Connects 249Ω resistor shunt to XFMR LOOP. …
246 | | | | Closed | | | Connects power to VDDIO. …
253 | | | | Closed | | | Connects power to VDDA. …
260 | | | | Closed | | | Connects power to VDD18. …
267 | | | | Closed | | | Connects power to VCORE. …
272 | | | | 2-1 | | | Connects OB_VREF to REF0P. …
274 | | | | 2-3 | | | Connects INT_VREF to REF0P. …
279 | | | | 2-1 | | | Connects OB_VREF to REF1P. …
281 | | | | 2-3 | | | Connects INT_VREF to REF1P. …
292 The HART circuitry acts as a secondary master with the ability to connect to an existing 4mA–20mA
293 current loop and communicates with HART-enabled devices. Connection to a capacitance coupled loop
294 through JH8 and a transformer loop is through JH9. HART communication to the MAX32675 is through
297 USB-to-HART Interface
299 The EV kit provides a USB-to-HART bridge chip, FTDI FT231. This bridge eliminates the requirement
314 To accurately achieve the low-power current values, the EVkit needs to be configured
330 The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates
332 the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0
353 The I2C port can independently pulled up to 3V3 through JP3 (I2C_SCL) and JP4 (I2C_SDA).
361 General-purpose indicators LED D1 (red) is connected to GPIO P1.9 and LED D2 (green) is connected
362 to GPIO P1.10.
366 The two general-purpose pushbuttons (SW1 and SW2) are connected to GPIO P1.11 and P1.12,
377 Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT)
378 is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect
381 Once the debug probe is connected to your host computer, then you can simply run the
382 ``west flash`` command to write a firmware image into flash. To perform a full erase,
389 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
390 be connected to the standard 2*5 pin debug connector (JH2) using an
396 Please refer to the `Flashing`_ section and run the ``west debug`` command