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6 of the MAX32655 microcontroller, which is an advanced system-on-chip (SoC).
7 It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and
9 Bluetooth® 5.0 Low Energy (Bluetooth LE), long-range radio for wearable and hearable device applica…
24 - MAX32655 MCU:
26 - Ultra-Low-Power Wireless Microcontroller
27 - Internal 100MHz Oscillator
28 - Flexible Low-Power Modes with 7.3728MHz System Clock Option
29 - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank)
30 - 16KB Instruction Cache
31 - Bluetooth 5.2 LE Radio
32 …- Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Proce…
33 - Fully Open-Source Bluetooth 5.2 Stack Available
34 - Supports AoA, AoD, LE Audio, and Mesh
35 - High-Throughput (2Mbps) Mode
36 - Long-Range (125kbps and 500kbps) Modes
37 - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm
38 - Single-Ended Antenna Connection (50Ω)
39 - Power Management Maximizes Battery Life
40 - 2.0V to 3.6V Supply Voltage Range
41 - Integrated SIMO Power Regulator
42 - Dynamic Voltage Scaling (DVS)
43 - 23.8μA/MHz Active Current at 3.0V
44 - 4.4μA at 3.0V Retention Current for 32KB
45 - Selectable SRAM Retention + RTC in Low-Power Modes
46 - Multiple Peripherals for System Control
47 - Up to Two High-Speed SPI Master/Slave
48 - Up to Three High-Speed I2C Master/Slave (3.4Mbps)
49 - Up to Four UART, One I2S Master/Slave
50 - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps
51 - Up to Four Micro-Power Comparators
52 - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers
53 - 1-Wire® Master
54 - Up to Four Pulse Train (PWM) Engines
55 - RTC with Wake-Up Timer
56 - Up to 52 GPIOs
57 - Security and Integrity
58 - Available Secure Boot
59 - TRNG Seed Generator
60 - AES 128/192/256 Hardware Acceleration Engine
62 - External devices connected to the MAX32655 EVKIT:
64 - Color TFT Display
65 - Audio Stereo Codec Interface
66 - Digital Microphone
67 - A 128Mb QSPI flash
74 +-----------+------------+-------------------------------------+
77 | NVIC | on-chip | nested vector interrupt controller |
78 +-----------+------------+-------------------------------------+
79 | SYSTICK | on-chip | systick |
80 +-----------+------------+-------------------------------------+
81 | CLOCK | on-chip | clock and reset control |
82 +-----------+------------+-------------------------------------+
83 | GPIO | on-chip | gpio |
84 +-----------+------------+-------------------------------------+
85 | UART | on-chip | serial |
86 +-----------+------------+-------------------------------------+
87 | TRNG | on-chip | entropy |
88 +-----------+------------+-------------------------------------+
89 | I2C | on-chip | i2c |
90 +-----------+------------+-------------------------------------+
91 | DMA | on-chip | dma controller |
92 +-----------+------------+-------------------------------------+
93 | Watchdog | on-chip | watchdog |
94 +-----------+------------+-------------------------------------+
95 | SPI | on-chip | spi |
96 +-----------+------------+-------------------------------------+
97 | ADC | on-chip | adc |
98 +-----------+------------+-------------------------------------+
99 | Timer | on-chip | counter |
100 +-----------+------------+-------------------------------------+
101 | PWM | on-chip | pwm |
102 +-----------+------------+-------------------------------------+
103 | W1 | on-chip | one wire master |
104 +-----------+------------+-------------------------------------+
105 | Flash | on-chip | flash |
106 +-----------+------------+-------------------------------------+
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168 SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH3.
177 a Segger J-Link with Segger's native tooling by overriding the runner,
178 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
191 - `MAX32655EVKIT web page`_
194 …https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ma…