Lines Matching refs:page
219 uint32_t page, *table; in map_memory_range() local
224 for (page = start; page < end; page += CONFIG_MMU_PAGE_SIZE) { in map_memory_range()
225 uint32_t pte = XTENSA_MMU_PTE(page, in map_memory_range()
229 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in map_memory_range()
230 uint32_t l1_pos = XTENSA_MMU_L1_POS(page); in map_memory_range()
236 "map 0x%08x\n", page); in map_memory_range()
362 uintptr_t page; in arch_reserved_pages_update() local
365 for (page = CONFIG_SRAM_BASE_ADDRESS, idx = 0; in arch_reserved_pages_update()
366 page < (uintptr_t)z_mapped_start; in arch_reserved_pages_update()
367 page += CONFIG_MMU_PAGE_SIZE, idx++) { in arch_reserved_pages_update()
858 uint32_t page = start + offset; in region_map_update() local
859 uint32_t l1_pos = XTENSA_MMU_L1_POS(page); in region_map_update()
860 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in region_map_update()
875 xtensa_dtlb_vaddr_invalidate((void *)page); in region_map_update()
1053 static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool write) in page_validate() argument
1057 uint32_t l1_pos = XTENSA_MMU_L1_POS(page); in page_validate()
1058 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in page_validate()