Lines Matching refs:l2_pos
229 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in map_memory_range() local
246 table[l2_pos] = pte; in map_memory_range()
370 uint32_t l2_pos = XTENSA_MMU_L2_POS((uint32_t)vaddr); in l2_page_table_map() local
391 table[l2_pos] = XTENSA_MMU_PTE(phys, is_user ? XTENSA_MMU_USER_RING : in l2_page_table_map()
395 sys_cache_data_flush_range((void *)&table[l2_pos], sizeof(table[0])); in l2_page_table_map()
536 uint32_t l2_pos = XTENSA_MMU_L2_POS((uint32_t)vaddr); in l2_page_table_unmap() local
554 sys_cache_data_invd_range((void *)&l2_table[l2_pos], sizeof(l2_table[0])); in l2_page_table_unmap()
556 l2_table[l2_pos] = XTENSA_MMU_PTE_ILLEGAL; in l2_page_table_unmap()
558 sys_cache_data_flush_range((void *)&l2_table[l2_pos], sizeof(l2_table[0])); in l2_page_table_unmap()
560 for (l2_pos = 0; l2_pos < XTENSA_L2_PAGE_TABLE_ENTRIES; l2_pos++) { in l2_page_table_unmap()
561 if (!is_pte_illegal(l2_table[l2_pos])) { in l2_page_table_unmap()
853 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in region_map_update() local
859 sys_cache_data_invd_range((void *)&l2_table[l2_pos], sizeof(l2_table[0])); in region_map_update()
861 pte = XTENSA_MMU_PTE_RING_SET(l2_table[l2_pos], ring); in region_map_update()
864 l2_table[l2_pos] = pte; in region_map_update()
866 sys_cache_data_flush_range((void *)&l2_table[l2_pos], sizeof(l2_table[0])); in region_map_update()
1051 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in page_validate() local
1058 pte = l2_table[l2_pos]; in page_validate()