Lines Matching refs:l1_table
366 static bool l2_page_table_map(uint32_t *l1_table, void *vaddr, uintptr_t phys, in l2_page_table_map() argument
373 sys_cache_data_invd_range((void *)&l1_table[l1_pos], sizeof(l1_table[0])); in l2_page_table_map()
375 if (is_pte_illegal(l1_table[l1_pos])) { in l2_page_table_map()
384 l1_table[l1_pos] = XTENSA_MMU_PTE((uint32_t)table, XTENSA_MMU_KERNEL_RING, in l2_page_table_map()
387 sys_cache_data_flush_range((void *)&l1_table[l1_pos], sizeof(l1_table[0])); in l2_page_table_map()
390 table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK); in l2_page_table_map()
533 static bool l2_page_table_unmap(uint32_t *l1_table, void *vaddr) in l2_page_table_unmap() argument
541 sys_cache_data_invd_range((void *)&l1_table[l1_pos], sizeof(l1_table[0])); in l2_page_table_unmap()
543 if (is_pte_illegal(l1_table[l1_pos])) { in l2_page_table_unmap()
550 exec = l1_table[l1_pos] & XTENSA_MMU_PERM_X; in l2_page_table_unmap()
552 l2_table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK); in l2_page_table_unmap()
566 l1_table[l1_pos] = XTENSA_MMU_PTE_ILLEGAL; in l2_page_table_unmap()
567 sys_cache_data_flush_range((void *)&l1_table[l1_pos], sizeof(l1_table[0])); in l2_page_table_unmap()