Lines Matching full:fifo
34 fifo-start-offset:
36 Each USIC0..2 has a fifo that is shared between two channels. For example,
37 usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset
38 where the tx and rx fifos will start. When sharing the fifo, the user must properly
39 define the offset based on the configuration of the other channel. The fifo has a
40 capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
46 fifo-tx-size:
48 Fifo size used for buffering transmit bytes. A value of 0 implies that
49 the fifo is not used while transmitting. transmitting. If the UART is used in async mode
50 then fifo-tx-size should be set to 0.
62 fifo-rx-size:
64 Fifo size used for buffering received bytes. A value of 0 implies that
65 the fifo is not used while receiving. If the UART is used in async mode
66 then fifo-rx-size should be set to 0.