Lines Matching +full:reg +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <DT_FREQ_K(125125)>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 reg = <0>;
41 hlic: interrupt-controller {
42 compatible = "riscv,cpu-intc";
43 #address-cells = <0>;
44 #interrupt-cells = <1>;
45 interrupt-controller;
51 mmu-type = "riscv,sv39";
52 reg = <0x1>;
55 cpu1_intc: interrupt-controller {
56 compatible = "riscv,cpu-intc";
57 #interrupt-cells = <1>;
58 interrupt-controller;
64 mmu-type = "riscv,sv39";
65 reg = <0x2>;
68 cpu2_intc: interrupt-controller {
69 compatible = "riscv,cpu-intc";
70 #interrupt-cells = <1>;
71 interrupt-controller;
77 mmu-type = "riscv,sv39";
78 reg = <0x3>;
81 cpu3_intc: interrupt-controller {
82 compatible = "riscv,cpu-intc";
83 #interrupt-cells = <1>;
84 interrupt-controller;
90 mmu-type = "riscv,sv39";
91 reg = <0x4>;
94 cpu4_intc: interrupt-controller {
95 compatible = "riscv,cpu-intc";
96 #interrupt-cells = <1>;
97 interrupt-controller;
103 #address-cells = <2>;
104 #size-cells = <2>;
105 compatible = "simple-bus";
110 reg = <0x0 0x1000 0x0 0x1000>;
111 reg-names = "mem";
116 reg = <0x0 0x10000 0x0 0x8000>;
117 reg-names = "mem";
122 reg = <0x0 0x1000000 0x0 0x2000>;
123 reg-names = "mem";
128 interrupts-extended = <&hlic 3 &hlic 7>;
129 reg = <0x0 0x2000000 0x0 0x10000>;
134 reg = <0x0 0x8000000 0x0 0x200000>;
135 reg-names = "mem";
139 plic: interrupt-controller@c000000 {
140 compatible = "sifive,plic-1.0.0";
141 #address-cells = <0>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 interrupts-extended = <&hlic 11>;
145 reg = <0x0 0x0c000000 0x0 0x04000000>;
146 riscv,max-priority = <7>;
152 interrupt-parent = <&plic>;
154 reg = <0x0 0x10010000 0x0 0x1000>;
155 reg-names = "control";
161 interrupt-parent = <&plic>;
163 reg = <0x0 0x10011000 0x0 0x1000>;
164 reg-names = "control";
170 interrupt-parent = <&plic>;
172 reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
173 reg-names = "control", "mem";
175 #address-cells = <1>;
176 #size-cells = <0>;
181 interrupt-parent = <&plic>;
183 reg = <0x0 0x10041000 0x0 0x1000>;
184 reg-names = "control";
186 #address-cells = <1>;
187 #size-cells = <0>;
192 interrupt-parent = <&plic>;
194 reg = <0x0 0x10050000 0x0 0x1000>;
195 reg-names = "control";
197 #address-cells = <1>;
198 #size-cells = <0>;
201 compatible = "sifive,fu740-c000-ddr";
202 reg = <0x0 0x100b0000 0x0 0x0800