Lines Matching +full:reg +full:- +full:names
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "litex,vexriscv", "litex-dev";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 clock-frequency = <100000000>;
25 reg = <0>;
28 timebase-frequency = <32768>;
32 #address-cells = <1>;
33 #size-cells = <1>;
36 intc0: interrupt-controller@bc0 {
37 compatible = "vexriscv-intc0";
38 #address-cells = <0>;
39 #interrupt-cells = <2>;
40 interrupt-controller;
41 reg = <0xbc0 0x4 0xfc0 0x4>;
42 reg-names = "irq_mask", "irq_pending";
43 riscv,max-priority = <7>;
47 interrupt-parent = <&intc0>;
49 reg = <0xe0001800 0x4
57 reg-names =
70 reg = <0xe0002000 0x4
76 reg-names = "control",
83 #address-cells = <1>;
84 #size-cells = <0>;
88 interrupt-parent = <&intc0>;
90 reg = <0xe0002800 0x4
100 reg-names =
115 interrupt-parent = <&intc0>;
117 reg = <0xe0009800 0x4
132 local-mac-address = [10 e2 d5 00 00 02];
133 reg-names = "rx_slot",
152 /* DNA data is 57-bits long,
154 In LiteX each 32-bit register holds
157 reg = <0xe0003800 0x20>;
158 reg-names = "mem";
163 reg = <0xe0005000 0x4 0xe0005004 0x4>;
164 reg-names = "write", "read";
165 #address-cells = <1>;
166 #size-cells = <0>;
171 reg = <0xe0005800 0x4>;
172 reg-names = "control";
174 port-is-output;
176 gpio-controller;
177 #gpio-cells = <2>;
181 reg = <0xe0006000 0x4
186 interrupt-parent = <&intc0>;
188 reg-names = "base",
195 gpio-controller;
196 #gpio-cells = <2>;
200 reg = <0xe0006800 0x4>;
201 reg-names = "status";
206 reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
207 reg-names = "enable", "width", "period";
209 #pwm-cells = <2>;
213 reg = <0xe000a800 0x4
220 interrupt-parent = <&intc0>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg-names = "ev_status",
236 reg = <0xe000b000 0x4
243 interrupt-parent = <&intc0>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 reg-names = "ev_status",
257 clock-outputs {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 clk0: clock-controller@0 {
261 #clock-cells = <1>;
262 reg = <0>;
264 clock-output-names = "CLK_0";
265 litex,clock-frequency = <11289600>;
266 litex,clock-phase = <0>;
267 litex,clock-duty-num = <1>;
268 litex,clock-duty-den = <2>;
269 litex,clock-margin = <1>;
270 litex,clock-margin-exp = <2>;
273 clk1: clock-controller@1 {
274 #clock-cells = <1>;
275 reg = <1>;
277 clock-output-names = "CLK_1";
278 litex,clock-frequency = <22579200>;
279 litex,clock-phase = <0>;
280 litex,clock-duty-num = <1>;
281 litex,clock-duty-den = <2>;
282 litex,clock-margin = <1>;
283 litex,clock-margin-exp = <2>;
289 reg = <0xe0004800 0x4
297 reg-names = "drp_reset",
305 #clock-cells = <1>;
307 clock-output-names = "CLK_0", "CLK_1";
308 litex,lock-timeout = <10>;
309 litex,drdy-timeout = <10>;
310 litex,sys-clock-frequency = <100000000>;
311 litex,divclk-divide-min = <1>;
312 litex,divclk-divide-max = <107>;
313 litex,clkfbout-mult-min = <2>;
314 litex,clkfbout-mult-max = <65>;
315 litex,vco-freq-min = <600000000>;
316 litex,vco-freq-max = <1200000000>;
317 litex,clkout-divide-min = <1>;
318 litex,clkout-divide-max = <126>;
319 litex,vco-margin = <0>;