Lines Matching +full:vw +full:- +full:reg
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4";
28 reg = <0>;
29 cpu-power-states = <&idle &suspend_to_ram>;
32 power-states {
34 compatible = "zephyr,power-state";
35 power-state-name = "suspend-to-idle";
36 min-residency-us = <1000000>;
40 compatible = "zephyr,power-state";
41 power-state-name = "suspend-to-ram";
42 min-residency-us = <2000000>;
48 reg = <0x000C0000 0x58000>;
52 compatible = "mmio-sram";
53 reg = <0x00118000 0x10000>;
58 reg = <0x4000fc00 0x200>;
61 compatible = "microchip,xec-pcr";
62 reg = <0x40080100 0x100 0x4000a400 0x100>;
63 reg-names = "pcrr", "vbatr";
65 core-clock-div = <1>;
67 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
68 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
69 clk32kmon-period-min = <1435>;
70 clk32kmon-period-max = <1495>;
71 clk32kmon-duty-cycle-var-max = <132>;
72 clk32kmon-valid-min = <4>;
73 xtal-enable-delay-ms = <300>;
74 pll-lock-timeout-ms = <30>;
76 pinctrl-0 = <&clk_32khz_in_gpio165>;
77 pinctrl-names = "default";
78 #clock-cells = <3>;
81 compatible = "microchip,xec-ecia";
82 reg = <0x4000e000 0x400>;
83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
85 #address-cells = <1>;
86 #size-cells = <1>;
91 compatible = "microchip,xec-ecia-girq";
92 reg = <0x0 0x14>;
94 girq-id = <0>;
102 compatible = "microchip,xec-ecia-girq";
103 reg = <0x14 0x14>;
105 girq-id = <1>;
113 compatible = "microchip,xec-ecia-girq";
114 reg = <0x28 0x14>;
116 girq-id = <2>;
124 compatible = "microchip,xec-ecia-girq";
125 reg = <0x3c 0x14>;
127 girq-id = <3>;
135 compatible = "microchip,xec-ecia-girq";
136 reg = <0x50 0x14>;
138 girq-id = <4>;
146 compatible = "microchip,xec-ecia-girq";
147 reg = <0x64 0x14>;
149 girq-id = <5>;
154 compatible = "microchip,xec-ecia-girq";
155 reg = <0x78 0x14>;
157 girq-id = <6>;
163 compatible = "microchip,xec-ecia-girq";
164 reg = <0x8c 0x14>;
166 girq-id = <7>;
173 compatible = "microchip,xec-ecia-girq";
174 reg = <0xa0 0x14>;
176 girq-id = <8>;
181 compatible = "microchip,xec-ecia-girq";
182 reg = <0xb4 0x14>;
184 girq-id = <9>;
190 compatible = "microchip,xec-ecia-girq";
191 reg = <0xc8 0x14>;
193 girq-id = <10>;
200 compatible = "microchip,xec-ecia-girq";
201 reg = <0xdc 0x14>;
203 girq-id = <11>;
208 compatible = "microchip,xec-ecia-girq";
209 reg = <0xf0 0x14>;
211 girq-id = <12>;
216 compatible = "microchip,xec-ecia-girq";
217 reg = <0x104 0x14>;
219 girq-id = <13>;
225 compatible = "microchip,xec-ecia-girq";
226 reg = <0x118 0x14>;
228 girq-id = <14>;
233 compatible = "microchip,xec-ecia-girq";
234 reg = <0x12c 0x14>;
236 girq-id = <15>;
241 compatible = "microchip,xec-ecia-girq";
242 reg = <0x140 0x14>;
244 girq-id = <16>;
251 compatible = "microchip,xec-ecia-girq";
252 reg = <0x154 0x14>;
254 girq-id = <17>;
260 compatible = "microchip,xec-ecia-girq";
261 reg = <0x168 0x14>;
263 girq-id = <18>;
268 pinctrl: pin-controller@40081000 {
269 compatible = "microchip,xec-pinctrl";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 reg = <0x40081000 0x1000>;
275 compatible = "microchip,xec-gpio-v2";
276 reg = < 0x40081000 0x80 0x40081300 0x04
279 gpio-controller;
280 port-id = <0>;
281 girq-id = <11>;
282 #gpio-cells=<2>;
285 compatible = "microchip,xec-gpio-v2";
286 reg = < 0x40081080 0x80 0x40081304 0x04
289 gpio-controller;
290 port-id = <1>;
291 girq-id = <10>;
292 #gpio-cells=<2>;
295 compatible = "microchip,xec-gpio-v2";
296 reg = < 0x40081100 0x80 0x40081308 0x04
298 gpio-controller;
300 port-id = <2>;
301 girq-id = <9>;
302 #gpio-cells=<2>;
305 compatible = "microchip,xec-gpio-v2";
306 reg = < 0x40081180 0x80 0x4008130c 0x04
308 gpio-controller;
310 port-id = <3>;
311 girq-id = <8>;
312 #gpio-cells=<2>;
315 compatible = "microchip,xec-gpio-v2";
316 reg = < 0x40081200 0x80 0x40081310 0x04
318 gpio-controller;
320 port-id = <4>;
321 girq-id = <12>;
322 #gpio-cells=<2>;
325 compatible = "microchip,xec-gpio-v2";
326 reg = < 0x40081280 0x80 0x40081314 0x04
328 gpio-controller;
330 port-id = <5>;
331 girq-id = <26>;
332 #gpio-cells=<2>;
336 compatible = "microchip,xec-watchdog";
337 reg = <0x40000400 0x400>;
343 compatible = "microchip,xec-rtos-timer";
344 reg = <0x40007400 0x10>;
349 compatible = "microchip,xec-timer";
350 clock-frequency = <48000000>;
351 reg = <0x40000c00 0x20>;
355 max-value = <0xFFFF>;
360 compatible = "microchip,xec-timer";
361 clock-frequency = <48000000>;
362 reg = <0x40000c20 0x20>;
366 max-value = <0xFFFF>;
371 compatible = "microchip,xec-timer";
372 clock-frequency = <48000000>;
373 reg = <0x40000c40 0x20>;
377 max-value = <0xFFFF>;
382 compatible = "microchip,xec-timer";
383 clock-frequency = <48000000>;
384 reg = <0x40000c60 0x20>;
388 max-value = <0xFFFF>;
398 compatible = "microchip,xec-timer";
399 clock-frequency = <48000000>;
400 reg = <0x40000c80 0x20>;
404 max-value = <0xFFFFFFFF>;
409 compatible = "microchip,xec-timer";
410 clock-frequency = <48000000>;
411 reg = <0x40000ca0 0x20>;
415 max-value = <0xFFFFFFFF>;
420 reg = <0x40000d00 0x20>;
427 reg = <0x40000d20 0x20>;
434 reg = <0x40000d40 0x20>;
441 reg = <0x40000d60 0x20>;
448 reg = <0x40001000 0x40>;
458 reg = <0x40009800 0x20>;
463 reg = <0x40009820 0x20>;
468 reg = <0x4000ac80 0x80>;
474 bbram: bb-ram@4000a800 {
475 compatible = "microchip,xec-bbram";
476 reg = <0x4000a800 0x100>;
477 reg-names = "memory";
480 reg = <0x4000ae00 0x40>;
487 compatible = "microchip,xec-dmac";
488 reg = <0x40002400 0xc00>;
510 #dma-cells = <2>;
511 dma-channels = <16>;
512 dma-requests = <16>;
516 compatible = "microchip,xec-eeprom";
517 reg = <0x40002c00 0x400>;
525 compatible = "microchip,xec-i2c-v2";
526 reg = <0x40004000 0x80>;
527 clock-frequency = <I2C_BITRATE_STANDARD>;
531 #address-cells = <1>;
532 #size-cells = <0>;
536 compatible = "microchip,xec-i2c-v2";
537 reg = <0x40004400 0x80>;
538 clock-frequency = <I2C_BITRATE_STANDARD>;
542 #address-cells = <1>;
543 #size-cells = <0>;
547 compatible = "microchip,xec-i2c-v2";
548 reg = <0x40004800 0x80>;
549 clock-frequency = <I2C_BITRATE_STANDARD>;
553 #address-cells = <1>;
554 #size-cells = <0>;
558 compatible = "microchip,xec-i2c-v2";
559 reg = <0x40004C00 0x80>;
560 clock-frequency = <I2C_BITRATE_STANDARD>;
564 #address-cells = <1>;
565 #size-cells = <0>;
569 compatible = "microchip,xec-i2c-v2";
570 reg = <0x40005000 0x80>;
571 clock-frequency = <I2C_BITRATE_STANDARD>;
575 #address-cells = <1>;
576 #size-cells = <0>;
580 compatible = "microchip,xec-ps2";
581 reg = <0x40009000 0x40>;
585 #address-cells = <1>;
586 #size-cells = <0>;
590 compatible = "microchip,xec-pwm";
591 reg = <0x40005800 0x20>;
594 #pwm-cells = <3>;
597 compatible = "microchip,xec-pwm";
598 reg = <0x40005810 0x20>;
601 #pwm-cells = <3>;
604 compatible = "microchip,xec-pwm";
605 reg = <0x40005820 0x20>;
608 #pwm-cells = <3>;
611 compatible = "microchip,xec-pwm";
612 reg = <0x40005830 0x20>;
615 #pwm-cells = <3>;
618 compatible = "microchip,xec-pwm";
619 reg = <0x40005840 0x20>;
622 #pwm-cells = <3>;
625 compatible = "microchip,xec-pwm";
626 reg = <0x40005850 0x20>;
629 #pwm-cells = <3>;
632 compatible = "microchip,xec-pwm";
633 reg = <0x40005860 0x20>;
636 #pwm-cells = <3>;
639 compatible = "microchip,xec-pwm";
640 reg = <0x40005870 0x20>;
643 #pwm-cells = <3>;
646 compatible = "microchip,xec-pwm";
647 reg = <0x40005880 0x20>;
650 #pwm-cells = <3>;
653 compatible = "microchip,xec-tach";
654 reg = <0x40006000 0x10>;
658 #address-cells = <1>;
659 #size-cells = <0>;
663 compatible = "microchip,xec-tach";
664 reg = <0x40006010 0x10>;
668 #address-cells = <1>;
669 #size-cells = <0>;
673 compatible = "microchip,xec-tach";
674 reg = <0x40006020 0x10>;
678 #address-cells = <1>;
679 #size-cells = <0>;
683 compatible = "microchip,xec-tach";
684 reg = <0x40006030 0x10>;
688 #address-cells = <1>;
689 #size-cells = <0>;
693 reg = <0x4000a000 0x80>;
700 reg = <0x4000a080 0x80>;
707 compatible = "microchip,xec-adc";
708 reg = <0x40007c00 0x90>;
713 #io-channel-cells = <1>;
717 compatible = "microchip,xec-kscan";
718 reg = <0x40009c00 0x18>;
723 #address-cells = <1>;
724 #size-cells = <0>;
727 compatible = "microchip,xec-peci";
728 reg = <0x40006400 0x80>;
732 #address-cells = <1>;
733 #size-cells = <0>;
736 reg = <0x40070000 0x400>;
740 clock-frequency = <12000000>;
742 chip-select = <0>;
743 #address-cells = <1>;
744 #size-cells = <0>;
748 reg = <0x40009400 0x80>;
755 reg = <0x40009480 0x80>;
762 reg = <0x40003400 0x20>;
769 reg = <0x40001400 0x80>;
776 reg = <0x40001480 0x80>;
783 reg = <0x40001500 0x80>;
790 reg = <0x40007000 0x100>;
797 reg = <0x4000b800 0x100>;
804 reg = <0x4000b900 0x100>;
811 reg = <0x4000ba00 0x100>;
818 reg = <0x4000bb00 0x100>;
825 reg = <0x4000cd00 0x20>;
832 reg = <0x40008c00 0x10>;
837 reg = <0x400fff00 0x40>;
842 compatible = "microchip,xec-uart";
843 reg = <0x400f2400 0x400>;
845 clock-frequency = <1843200>;
846 current-speed = <38400>;
853 compatible = "microchip,xec-uart";
854 reg = <0x400f2800 0x400>;
856 clock-frequency = <1843200>;
857 current-speed = <38400>;
864 compatible = "microchip,xec-espi-v2";
865 /* reg tuple contains one 32-bit address cell and one
866 * 32-bit length(size) cell.
868 #address-cells = <1>;
869 #size-cells = <1>;
870 reg = < 0x400f3400 0x400
873 reg-names = "io", "mem", "vw";
877 interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up",
892 compatible = "microchip,xec-espi-saf-v2";
893 reg = <0x40008000 0x400>, <0x40070000 0x400>,
895 reg-names = "safbr", "safqspi", "safcomm";
897 interrupt-names = "done", "err";
905 compatible = "microchip,xec-espi-host-dev";
906 reg = <0x400f0000 0x200>;
914 compatible = "microchip,xec-espi-host-dev";
915 reg = <0x400f0400 0x400>;
917 interrupt-names = "kbc_obe", "kbc_ibf";
924 compatible = "microchip,xec-espi-host-dev";
925 reg = <0x400f0800 0x400>;
927 interrupt-names = "acpi_ibf", "acpi_obe";
934 compatible = "microchip,xec-espi-host-dev";
935 reg = <0x400f0c00 0x400>;
937 interrupt-names = "acpi_ibf", "acpi_obe";
944 compatible = "microchip,xec-espi-host-dev";
945 reg = <0x400f1000 0x400>;
947 interrupt-names = "acpi_ibf", "acpi_obe";
954 compatible = "microchip,xec-espi-host-dev";
955 reg = <0x400f1400 0x400>;
957 interrupt-names = "acpi_ibf", "acpi_obe";
964 compatible = "microchip,xec-espi-host-dev";
965 reg = <0x400f1800 0x400>;
967 interrupt-names = "acpi_ibf", "acpi_obe";
974 compatible = "microchip,xec-espi-host-dev";
975 reg = <0x400f1c00 0x400>;
977 interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts";
985 compatible = "microchip,xec-espi-host-dev";
986 reg = <0x400f2000 0x400>;
991 compatible = "microchip,xec-espi-host-dev";
992 reg = <0x400f4000 0x400>;
999 compatible = "microchip,xec-espi-host-dev";
1000 reg = <0x400f4400 0x400>;
1007 compatible = "microchip,xec-espi-host-dev";
1008 reg = <0x400f4800 0x400>;
1015 compatible = "microchip,xec-espi-host-dev";
1016 reg = <0x400f5000 0x100>;
1024 /* Capture writes to host I/O 0x80 - 0x83 */
1026 compatible = "microchip,xec-espi-host-dev";
1027 reg = <0x400f8000 0x400>;
1034 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */
1036 compatible = "microchip,xec-espi-host-dev";
1037 reg = <0x400f8400 0x400>;
1039 host-io = <0x90>;
1041 host-io-addr-mask = <0x01>;
1047 compatible = "microchip,xec-symcr";
1048 reg = <0x40100000 0x1000>;
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1058 reg = <0x1f000 0x1000>;
1065 arm,num-irq-priority-bits = <3>;