Lines Matching +full:reg +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 zephyr,flash-controller = &nvmctrl;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
25 reg = <0>;
26 #address-cells = <1>;
27 #size-cells = <1>;
30 compatible = "arm,armv7m-mpu";
31 reg = <0xe000ed90 0x40>;
32 arm,num-mpu-regions = <8>;
38 adc-0 = &adc0;
39 adc-1 = &adc1;
41 port-a = &porta;
42 port-b = &portb;
43 port-c = &portc;
44 port-d = &portd;
46 sercom-0 = &sercom0;
47 sercom-1 = &sercom1;
48 sercom-2 = &sercom2;
49 sercom-3 = &sercom3;
50 sercom-4 = &sercom4;
51 sercom-5 = &sercom5;
52 sercom-6 = &sercom6;
53 sercom-7 = &sercom7;
55 tc-0 = &tc0;
56 tc-2 = &tc2;
57 tc-4 = &tc4;
58 tc-6 = &tc6;
60 tcc-0 = &tcc0;
61 tcc-1 = &tcc1;
62 tcc-2 = &tcc2;
63 tcc-3 = &tcc3;
64 tcc-4 = &tcc4;
75 compatible = "mmio-sram";
76 reg = <0x20000000 0x40000>;
80 compatible = "mmio-sram";
81 reg = <0x47000000 0x2000>;
85 compatible = "atmel,sam0-id";
86 reg = <0x008061FC 0x4>,
93 compatible = "atmel,samd5x-mclk";
94 reg = <0x40000800 0x400>;
95 #clock-cells = <2>;
99 compatible = "atmel,samd5x-gclk";
100 reg = <0x40001c00 0x400>;
101 #clock-cells = <1>;
105 compatible = "atmel,sam0-nvmctrl";
106 reg = <0x41004000 0x22>;
108 lock-regions = <32>;
110 #address-cells = <1>;
111 #size-cells = <1>;
114 compatible = "soc-nv-flash";
115 write-block-size = <8>;
120 compatible = "atmel,sam0-dmac";
121 reg = <0x4100A000 0x50>;
123 #dma-cells = <2>;
127 compatible = "atmel,sam0-eic";
128 reg = <0x40002800 0x38>;
136 compatible = "atmel,sam0-pinmux";
137 reg = <0x41008000 0x80>;
141 compatible = "atmel,sam0-pinmux";
142 reg = <0x41008080 0x80>;
146 compatible = "atmel,sam0-pinmux";
147 reg = <0x41008100 0x80>;
151 compatible = "atmel,sam0-pinmux";
152 reg = <0x41008180 0x80>;
156 compatible = "atmel,sam0-watchdog";
157 reg = <0x40002000 13>;
162 compatible = "atmel,sam0-sercom";
163 reg = <0x40003000 0x40>;
167 clock-names = "GCLK", "MCLK";
171 compatible = "atmel,sam0-sercom";
172 reg = <0x40003400 0x40>;
176 clock-names = "GCLK", "MCLK";
180 compatible = "atmel,sam0-sercom";
181 reg = <0x41012000 0x40>;
185 clock-names = "GCLK", "MCLK";
189 compatible = "atmel,sam0-sercom";
190 reg = <0x41014000 0x40>;
194 clock-names = "GCLK", "MCLK";
198 compatible = "atmel,sam0-sercom";
199 reg = <0x43000000 0x40>;
203 clock-names = "GCLK", "MCLK";
207 compatible = "atmel,sam0-sercom";
208 reg = <0x43000400 0x40>;
212 clock-names = "GCLK", "MCLK";
216 compatible = "atmel,sam0-sercom";
217 reg = <0x43000800 0x40>;
221 clock-names = "GCLK", "MCLK";
225 compatible = "atmel,sam0-sercom";
226 reg = <0x43000C00 0x40>;
230 clock-names = "GCLK", "MCLK";
234 compatible = "atmel,sam0-pinctrl";
235 #address-cells = <1>;
236 #size-cells = <1>;
240 compatible = "atmel,sam0-gpio";
241 reg = <0x41008000 0x80>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 #atmel,pin-cells = <2>;
248 compatible = "atmel,sam0-gpio";
249 reg = <0x41008080 0x80>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 #atmel,pin-cells = <2>;
256 compatible = "atmel,sam0-gpio";
257 reg = <0x41008100 0x80>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 #atmel,pin-cells = <2>;
264 compatible = "atmel,sam0-gpio";
265 reg = <0x41008180 0x80>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 #atmel,pin-cells = <2>;
273 compatible = "atmel,sam0-usb";
275 reg = <0x41000000 0x1000>;
277 num-bidir-endpoints = <8>;
281 compatible = "atmel,sam-trng";
282 reg = <0x42002800 0x1e>;
287 compatible = "atmel,sam0-rtc";
288 reg = <0x40002400 0x1C>;
290 clock-generator = <0>;
295 compatible = "atmel,sam0-adc";
296 reg = <0x43001C00 0x4A>;
298 interrupt-names = "overrun", "resrdy";
302 * - table 54-8, section 54.6, page 2020
303 * - table 54-24, section 54.10.4, page 2031
304 * -> 48 MHz GCLK(2) / 4 = 12 MHz
308 #io-channel-cells = <1>;
310 clock-names = "GCLK", "MCLK";
311 calib-offset = <0>;
315 compatible = "atmel,sam0-adc";
316 reg = <0x43002000 0x4A>;
318 interrupt-names = "overrun", "resrdy";
322 * - table 54-8, section 54.6, page 2020
323 * - table 54-24, section 54.10.4, page 2031
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
328 #io-channel-cells = <1>;
330 clock-names = "GCLK", "MCLK";
331 calib-offset = <14>;
335 compatible = "atmel,sam0-tc32";
336 reg = <0x40003800 0x34>;
339 clock-names = "GCLK", "MCLK";
343 compatible = "atmel,sam0-tc32";
344 reg = <0x4101A000 0x34>;
347 clock-names = "GCLK", "MCLK";
351 compatible = "atmel,sam0-tc32";
352 reg = <0x42001400 0x34>;
355 clock-names = "GCLK", "MCLK";
359 compatible = "atmel,sam0-tc32";
360 reg = <0x43001400 0x34>;
363 clock-names = "GCLK", "MCLK";
367 compatible = "atmel,sam0-tcc";
368 reg = <0x41016000 0x2000>;
372 clock-names = "GCLK", "MCLK";
374 counter-size = <24>;
378 compatible = "atmel,sam0-tcc";
379 reg = <0x41018000 0x2000>;
382 clock-names = "GCLK", "MCLK";
384 counter-size = <24>;
388 compatible = "atmel,sam0-tcc";
389 reg = <0x42000c00 0x400>;
392 clock-names = "GCLK", "MCLK";
394 counter-size = <16>;
398 compatible = "atmel,sam0-tcc";
399 reg = <0x42001000 0x400>;
402 clock-names = "GCLK", "MCLK";
404 counter-size = <16>;
408 compatible = "atmel,sam0-tcc";
409 reg = <0x43001000 0x400>;
412 clock-names = "GCLK", "MCLK";
414 counter-size = <16>;
420 arm,num-irq-priority-bits = <3>;