1/*
2 * Copyright (c) 2019 ML!PA Consulting GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12
13/ {
14	chosen {
15		zephyr,flash-controller = &nvmctrl;
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			#address-cells = <1>;
27			#size-cells = <1>;
28
29			mpu: mpu@e000ed90 {
30				compatible = "arm,armv7m-mpu";
31				reg = <0xe000ed90 0x40>;
32				arm,num-mpu-regions = <8>;
33			};
34		};
35	};
36
37	aliases {
38		adc-0 = &adc0;
39		adc-1 = &adc1;
40
41		port-a = &porta;
42		port-b = &portb;
43		port-c = &portc;
44		port-d = &portd;
45
46		sercom-0 = &sercom0;
47		sercom-1 = &sercom1;
48		sercom-2 = &sercom2;
49		sercom-3 = &sercom3;
50		sercom-4 = &sercom4;
51		sercom-5 = &sercom5;
52		sercom-6 = &sercom6;
53		sercom-7 = &sercom7;
54
55		tc-0 = &tc0;
56		tc-2 = &tc2;
57		tc-4 = &tc4;
58		tc-6 = &tc6;
59
60		tcc-0 = &tcc0;
61		tcc-1 = &tcc1;
62		tcc-2 = &tcc2;
63		tcc-3 = &tcc3;
64		tcc-4 = &tcc4;
65
66		watchdog0 = &wdog;
67	};
68
69	chosen {
70		zephyr,entropy = &trng;
71	};
72
73	soc {
74		sram0: memory@20000000 {
75			compatible = "mmio-sram";
76			reg = <0x20000000 0x40000>;
77		};
78
79		backup0: memory@47000000 {
80			compatible = "mmio-sram";
81			reg = <0x47000000 0x2000>;
82		};
83
84		id: device_id@8061fc {
85			compatible = "atmel,sam0-id";
86			reg =	<0x008061FC 0x4>,
87				<0x00806010 0x4>,
88				<0x00806014 0x4>,
89				<0x00806018 0x4>;
90		};
91
92		mclk: mclk@40000800 {
93			compatible = "atmel,samd5x-mclk";
94			reg = <0x40000800 0x400>;
95			#clock-cells = <2>;
96		};
97
98		gclk: gclk@40001c00 {
99			compatible = "atmel,samd5x-gclk";
100			reg = <0x40001c00 0x400>;
101			#clock-cells = <1>;
102		};
103
104		nvmctrl: nvmctrl@41004000  {
105			compatible = "atmel,sam0-nvmctrl";
106			reg = <0x41004000 0x22>;
107			interrupts = <29 0>, <30 0>;
108			lock-regions = <32>;
109
110			#address-cells = <1>;
111			#size-cells = <1>;
112
113			flash0: flash@0 {
114				compatible = "soc-nv-flash";
115				write-block-size = <8>;
116			};
117		};
118
119		dmac: dmac@4100a000 {
120			compatible = "atmel,sam0-dmac";
121			reg = <0x4100A000 0x50>;
122			interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
123			#dma-cells = <2>;
124		};
125
126		eic: eic@40002800 {
127			compatible = "atmel,sam0-eic";
128			reg = <0x40002800 0x38>;
129			interrupts = <12 0>, <13 0>, <14 0>, <15 0>,
130				     <16 0>, <17 0>, <18 0>, <19 0>,
131				     <20 0>, <21 0>, <22 0>, <23 0>,
132				     <24 0>, <25 0>, <26 0>, <27 0>;
133		};
134
135		pinmux_a: pinmux@41008000 {
136			compatible = "atmel,sam0-pinmux";
137			reg = <0x41008000 0x80>;
138		};
139
140		pinmux_b: pinmux@41008080 {
141			compatible = "atmel,sam0-pinmux";
142			reg = <0x41008080 0x80>;
143		};
144
145		pinmux_c: pinmux@41008100 {
146			compatible = "atmel,sam0-pinmux";
147			reg = <0x41008100 0x80>;
148		};
149
150		pinmux_d: pinmux@41008180 {
151			compatible = "atmel,sam0-pinmux";
152			reg = <0x41008180 0x80>;
153		};
154
155		wdog: watchdog@40002000 {
156			compatible = "atmel,sam0-watchdog";
157			reg = <0x40002000 13>;
158			interrupts = <10 0>;
159		};
160
161		sercom0: sercom@40003000 {
162			compatible = "atmel,sam0-sercom";
163			reg = <0x40003000 0x40>;
164			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
165			status = "disabled";
166			clocks = <&gclk 7>, <&mclk 0x14 12>;
167			clock-names = "GCLK", "MCLK";
168		};
169
170		sercom1: sercom@40003400 {
171			compatible = "atmel,sam0-sercom";
172			reg = <0x40003400 0x40>;
173			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
174			status = "disabled";
175			clocks = <&gclk 8>, <&mclk 0x14 13>;
176			clock-names = "GCLK", "MCLK";
177		};
178
179		sercom2: sercom@41012000 {
180			compatible = "atmel,sam0-sercom";
181			reg = <0x41012000 0x40>;
182			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
183			status = "disabled";
184			clocks = <&gclk 23>, <&mclk 0x18 9>;
185			clock-names = "GCLK", "MCLK";
186		};
187
188		sercom3: sercom@41014000 {
189			compatible = "atmel,sam0-sercom";
190			reg = <0x41014000 0x40>;
191			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
192			status = "disabled";
193			clocks = <&gclk 24>, <&mclk 0x18 10>;
194			clock-names = "GCLK", "MCLK";
195		};
196
197		sercom4: sercom@43000000 {
198			compatible = "atmel,sam0-sercom";
199			reg = <0x43000000 0x40>;
200			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
201			status = "disabled";
202			clocks = <&gclk 34>, <&mclk 0x20 0>;
203			clock-names = "GCLK", "MCLK";
204		};
205
206		sercom5: sercom@43000400 {
207			compatible = "atmel,sam0-sercom";
208			reg = <0x43000400 0x40>;
209			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
210			status = "disabled";
211			clocks = <&gclk 35>, <&mclk 0x20 1>;
212			clock-names = "GCLK", "MCLK";
213		};
214
215		sercom6: sercom@43000800 {
216			compatible = "atmel,sam0-sercom";
217			reg = <0x43000800 0x40>;
218			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
219			status = "disabled";
220			clocks = <&gclk 36>, <&mclk 0x20 2>;
221			clock-names = "GCLK", "MCLK";
222		};
223
224		sercom7: sercom@43000c00 {
225			compatible = "atmel,sam0-sercom";
226			reg = <0x43000C00 0x40>;
227			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
228			status = "disabled";
229			clocks = <&gclk 37>, <&mclk 0x20 3>;
230			clock-names = "GCLK", "MCLK";
231		};
232
233		pinctrl: pinctrl@41008000 {
234			compatible = "atmel,sam0-pinctrl";
235			#address-cells = <1>;
236			#size-cells = <1>;
237			ranges = <0x41008000 0x41008000 0x200>;
238
239			porta: gpio@41008000 {
240				compatible = "atmel,sam0-gpio";
241				reg = <0x41008000 0x80>;
242				gpio-controller;
243				#gpio-cells = <2>;
244				#atmel,pin-cells = <2>;
245			};
246
247			portb: gpio@41008080 {
248				compatible = "atmel,sam0-gpio";
249				reg = <0x41008080 0x80>;
250				gpio-controller;
251				#gpio-cells = <2>;
252				#atmel,pin-cells = <2>;
253			};
254
255			portc: gpio@41008100 {
256				compatible = "atmel,sam0-gpio";
257				reg = <0x41008100 0x80>;
258				gpio-controller;
259				#gpio-cells = <2>;
260				#atmel,pin-cells = <2>;
261			};
262
263			portd: gpio@41008180 {
264				compatible = "atmel,sam0-gpio";
265				reg = <0x41008180 0x80>;
266				gpio-controller;
267				#gpio-cells = <2>;
268				#atmel,pin-cells = <2>;
269			};
270		};
271
272		usb0: usb@41000000 {
273			compatible = "atmel,sam0-usb";
274			status = "disabled";
275			reg = <0x41000000 0x1000>;
276			interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
277			num-bidir-endpoints = <8>;
278		};
279
280		trng: random@42002800 {
281			compatible = "atmel,sam-trng";
282			reg = <0x42002800 0x1e>;
283			interrupts = <131 0>;
284		};
285
286		rtc: rtc@40002400 {
287			compatible = "atmel,sam0-rtc";
288			reg = <0x40002400 0x1C>;
289			interrupts = <11 0>;
290			clock-generator = <0>;
291			status = "disabled";
292		};
293
294		adc0: adc@43001c00 {
295			compatible = "atmel,sam0-adc";
296			reg = <0x43001C00 0x4A>;
297			interrupts = <118 0>, <119 0>;
298			interrupt-names = "overrun", "resrdy";
299
300			/*
301			 * 16 MHz max, source clock must not exceed 100 MHz.
302			 *	- table 54-8, section 54.6, page 2020
303			 *	- table 54-24, section 54.10.4, page 2031
304			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
305			 */
306			gclk = <2>;
307			prescaler = <4>;
308			#io-channel-cells = <1>;
309			clocks = <&gclk 40>, <&mclk 0x20 7>;
310			clock-names = "GCLK", "MCLK";
311			calib-offset = <0>;
312		};
313
314		adc1: adc@43002000 {
315			compatible = "atmel,sam0-adc";
316			reg = <0x43002000 0x4A>;
317			interrupts = <120 0>, <121 0>;
318			interrupt-names = "overrun", "resrdy";
319
320			/*
321			 * 16 MHz max, source clock must not exceed 100 MHz.
322			 *	- table 54-8, section 54.6, page 2020
323			 *	- table 54-24, section 54.10.4, page 2031
324			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
325			 */
326			gclk = <2>;
327			prescaler = <4>;
328			#io-channel-cells = <1>;
329			clocks = <&gclk 41>, <&mclk 0x20 8>;
330			clock-names = "GCLK", "MCLK";
331			calib-offset = <14>;
332		};
333
334		tc0: tc@40003800 {
335			compatible = "atmel,sam0-tc32";
336			reg = <0x40003800 0x34>;
337			interrupts = <107 0>;
338			clocks = <&gclk 9>, <&mclk 0x14 14>;
339			clock-names = "GCLK", "MCLK";
340		};
341
342		tc2: tc@4101a000 {
343			compatible = "atmel,sam0-tc32";
344			reg = <0x4101A000 0x34>;
345			interrupts = <109 0>;
346			clocks = <&gclk 26>, <&mclk 0x18 13>;
347			clock-names = "GCLK", "MCLK";
348		};
349
350		tc4: tc@42001400 {
351			compatible = "atmel,sam0-tc32";
352			reg = <0x42001400 0x34>;
353			interrupts = <111 0>;
354			clocks = <&gclk 30>, <&mclk 0x1c 5>;
355			clock-names = "GCLK", "MCLK";
356		};
357
358		tc6: tc@43001400 {
359			compatible = "atmel,sam0-tc32";
360			reg = <0x43001400 0x34>;
361			interrupts = <113 0>;
362			clocks = <&gclk 39>, <&mclk 0x20 5>;
363			clock-names = "GCLK", "MCLK";
364		};
365
366		tcc0: tcc@41016000 {
367			compatible = "atmel,sam0-tcc";
368			reg = <0x41016000 0x2000>;
369			interrupts = <85 0>, <86 0>, <87 0>, <88 0>, <89 0>,
370				     <90 0>, <91 0>;
371			clocks = <&gclk 25>, <&mclk 0x18 11>;
372			clock-names = "GCLK", "MCLK";
373			channels = <6>;
374			counter-size = <24>;
375		};
376
377		tcc1: tcc@41018000 {
378			compatible = "atmel,sam0-tcc";
379			reg = <0x41018000 0x2000>;
380			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
381			clocks = <&gclk 25>, <&mclk 0x18 12>;
382			clock-names = "GCLK", "MCLK";
383			channels = <4>;
384			counter-size = <24>;
385		};
386
387		tcc2: tcc@42000c00 {
388			compatible = "atmel,sam0-tcc";
389			reg = <0x42000c00 0x400>;
390			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
391			clocks = <&gclk 29>, <&mclk 0x1c 3>;
392			clock-names = "GCLK", "MCLK";
393			channels = <3>;
394			counter-size = <16>;
395		};
396
397		tcc3: tcc@42001000 {
398			compatible = "atmel,sam0-tcc";
399			reg = <0x42001000 0x400>;
400			interrupts = <101 0>, <102 0>, <103 0>;
401			clocks = <&gclk 29>, <&mclk 0x1c 4>;
402			clock-names = "GCLK", "MCLK";
403			channels = <2>;
404			counter-size = <16>;
405		};
406
407		tcc4: tcc@43001000 {
408			compatible = "atmel,sam0-tcc";
409			reg = <0x43001000 0x400>;
410			interrupts = <104 0>, <105 0>, <106 0>;
411			clocks = <&gclk 38>, <&mclk 0x20 4>;
412			clock-names = "GCLK", "MCLK";
413			channels = <2>;
414			counter-size = <16>;
415		};
416	};
417};
418
419&nvic {
420	arm,num-irq-priority-bits = <3>;
421};
422