1 /* 2 * boot.h 3 * 4 * Created on: Jan 12, 2011 5 * Author: MIPS TECHNOLOGIES, INC 6 */ 7 /* 8 Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved 9 under the copyright laws of the United States of America and other countries. 10 11 This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and 12 may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party. 13 Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is 14 not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly 15 prohibited. At a minimum, this code is protected under trade secret, unfair competition, and 16 copyright laws. Violations thereof may result in criminal penalties and fines. 17 18 MIPS Technologies reserves the right to change this code to improve function, design or 19 otherwise. MIPS Technologies does not assume any liability arising out of the application or use 20 of this code, or of any error or omission in such code. Any warranties, whether express, statutory, 21 implied or otherwise, including but not limited to the implied warranties of merchantability or 22 fitness for a particular purpose, are excluded. Except as expressly provided in any written license 23 agreement from MIPS Technologies or an authorized third party, the furnishing of this code does 24 not give recipient any license to any intellectual property rights, including any patent rights, that 25 cover this code. 26 27 This code shall not be exported, reexported, transferred, or released, directly or indirectly, in 28 violation of the law of any country or international law, regulation, treaty, Executive Order, 29 statute, amendments or supplements thereto. Should a conflict arise regarding the export, 30 reexport, transfer, or release of this code, the laws of the United States of America shall be 31 the governing law. 32 33 This code may only be disclosed to the United States government ("Government"), or to 34 Government users, with prior written consent from MIPS Technologies or an authorized third 35 party. This code constitutes one or more of the following: commercial computer software, 36 commercial computer software documentation or other commercial items. If the user of this 37 code, or any related documentation of any kind, including related technical data or manuals, is an 38 agency, department, or other entity of the Government, the use, duplication, reproduction, release, 39 modification, disclosure, or transfer of this code, or any related documentation of any kind, is 40 restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and 41 Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of 42 this code by the Government is further restricted in accordance with the terms of the license 43 agreement(s) and/or applicable contract terms and conditions covering this code from MIPS 44 Technologies or an authorized third party. 45 */ 46 #define LEAF(name)\ 47 .##text;\ 48 .##globl name;\ 49 .##ent name;\ 50 name: 51 52 #define END(name)\ 53 .##size name,.-name;\ 54 .##end name 55 56 #define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG0 address of the GCR registers 57 #define GIC_P_BASE_ADDR 0x1bdc0000 // physical address of the GIC 58 #define GIC_BASE_ADDR 0xbbdc0000 // KSEG0 address address of the GIC 59 #define CPC_P_BASE_ADDR 0x1bde0001 // physical address of the CPC 60 #define CPC_BASE_ADDR 0xbbde0000 // KSEG0 address address of the CPC 61 62 #define DENALI_CTL_SECTION 0xbbc00000 63 #define MALTA_DISP_ADDR 0xbf000410 64 65 #define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */ 66 #define STACK_SIZE_LOG2 22 /* 4Mbytes each */ 67 68 69 /************************************************************************************** 70 Register use while executing in this file: ("GLOBAL" denotes a common value.) 71 **************************************************************************************/ 72 73 #define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */ 74 75 // $2 - $7 (v0, v1 a0 - a3) reserved for program use 76 77 #define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */ 78 #define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */ 79 #define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */ 80 #define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */ 81 82 // $12 - $15 (t4 - t7) are free to use 83 // $16, $17 (s0 and s1) reserved for program use 84 85 #define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */ 86 #define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */ 87 #define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */ 88 #define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */ 89 #define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */ 90 #define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */ 91 #define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */ 92 #define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */ 93 #define r26_int_addr $26 /* k0 Interrupt handler scratch address. */ 94 #define r27_int_data $27 /* k1 Interrupt handler scratch data. */ 95 // $28 gp and $29 sp 96 #define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */ 97 // $31 ra 98 99 100
