1 /* This file is part of the CodeSourcery C Library (CSLIBC). 2 3 Copyright (c) 2009 CodeSourcery, Inc. 4 5 THIS FILE CONTAINS PROPRIETARY, CONFIDENTIAL, AND TRADE SECRET 6 INFORMATION OF CODESOURCERY AND/OR ITS LICENSORS. 7 8 You may not use, modify or distribute this file without the express 9 written permission of CodeSourcery or its authorized 10 distributor. Please consult your license agreement for the 11 applicable terms and conditions. */ 12 13 /* 14 * Copyright (c) 1999-2007 MIPS Technologies, Inc. 15 * Copyright (C) 2009 CodeSourcery, LLC. 16 * 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * * Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * * Redistributions in binary form must reproduce the above 26 * copyright 27 * notice, this list of conditions and the following disclaimer 28 * in the documentation and/or other materials provided with 29 * the distribution. 30 * * Neither the name of MIPS Technologies Inc. nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 */ 46 47 /* 48 * m32c0.h : MIPS32 coprocessor 0 definitions 49 */ 50 51 52 #ifndef _M32C0_H_ 53 #define _M32C0_H_ 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 /* MIPS32-specific MMU interface */ 60 //#assert mmu(m32) 61 //#include "mips/m32tlb.h" 62 63 /* 64 * MIPS32 Exception Codes 65 */ 66 #define EXC_INTR 0 /* interrupt */ 67 #define EXC_MOD 1 /* tlb modification */ 68 #define EXC_TLBL 2 /* tlb miss (load/i-fetch) */ 69 #define EXC_TLBS 3 /* tlb miss (store) */ 70 #define EXC_ADEL 4 /* address error (load/i-fetch) */ 71 #define EXC_ADES 5 /* address error (store) */ 72 #define EXC_IBE 6 /* bus error (i-fetch) */ 73 #define EXC_DBE 7 /* data bus error (load/store) */ 74 #define EXC_SYS 8 /* system call */ 75 #define EXC_BP 9 /* breakpoint */ 76 #define EXC_RI 10 /* reserved instruction */ 77 #define EXC_CPU 11 /* coprocessor unusable */ 78 #define EXC_OVF 12 /* integer overflow */ 79 #define EXC_TRAP 13 /* trap exception */ 80 #define EXC_RES14 14 81 #define EXC_FPE 15 /* floating point exception */ 82 #define EXC_IS1 16 /* implementation-specific 1 */ 83 #define EXC_IS2 17 /* implementation-specific 2 */ 84 #define EXC_C2E 18 /* coprocessor 2 exception */ 85 #define EXC_RES19 19 86 #define EXC_RES20 20 87 #define EXC_RES21 21 88 #define EXC_MDMX 22 /* mdmx unusable */ 89 #define EXC_WATCH 23 /* watchpoint */ 90 #define EXC_MCHECK 24 /* machine check */ 91 #define EXC_THREAD 25 /* thread */ 92 #define EXC_DSPU 26 /* dsp unusable */ 93 #define EXC_RES27 27 94 #define EXC_RES28 28 95 #define EXC_RES29 29 96 #define EXC_RES30 30 97 #define EXC_RES31 31 98 99 100 /* 101 * MIPS32 Cause Register (CP0 Register 13, Select 0) 102 */ 103 #define CR_BD 0x80000000 /* branch delay */ 104 #define CR_TI 0x40000000 /* timer interrupt (r2) */ 105 #define CR_CEMASK 0x30000000 /* coprocessor used */ 106 #define CR_CESHIFT 28 107 #define CR_DC 0x08000000 /* disable count (r2) */ 108 #define CR_PCI 0x04000000 /* performance counter i/u (r2) */ 109 #define CR_IV 0x00800000 /* use special i/u vec */ 110 #define CR_WP 0x00400000 /* deferred watchpoint */ 111 112 /* interrupt pending bits */ 113 #define CR_SINT0 0x00000100 /* s/w interrupt 0 */ 114 #define CR_SINT1 0x00000200 /* s/w interrupt 1 */ 115 #define CR_HINT0 0x00000400 /* h/w interrupt 0 */ 116 #define CR_HINT1 0x00000800 /* h/w interrupt 1 */ 117 #define CR_HINT2 0x00001000 /* h/w interrupt 2 */ 118 #define CR_HINT3 0x00002000 /* h/w interrupt 3 */ 119 #define CR_HINT4 0x00004000 /* h/w interrupt 4 */ 120 #define CR_HINT5 0x00008000 /* h/w interrupt 5 */ 121 122 /* alternative interrupt pending bit naming */ 123 #define CR_IP0 0x00000100 124 #define CR_IP1 0x00000200 125 #define CR_IP2 0x00000400 126 #define CR_IP3 0x00000800 127 #define CR_IP4 0x00001000 128 #define CR_IP5 0x00002000 129 #define CR_IP6 0x00004000 130 #define CR_IP7 0x00008000 131 132 #define CR_IMASK 0x0000ff00 /* interrupt pending mask */ 133 #define CR_XMASK 0x0000007c /* exception code mask */ 134 #define CR_XCPT(x) ((x)<<2) 135 136 137 /* 138 * MIPS32 Status Register (CP0 Register 12, Select 0) 139 */ 140 #define SR_IE 0x00000001 /* interrupt enable */ 141 #define SR_EXL 0x00000002 /* exception level */ 142 #define SR_ERL 0x00000004 /* error level */ 143 144 #define SR_UM 0x00000010 /* user mode */ 145 #define SR_KSU_MASK 0x00000018 /* ksu mode mask */ 146 #define SR_KSU_USER 0x00000010 /* user mode */ 147 #define SR_KSU_SPVS 0x00000008 /* supervisor mode */ 148 #define SR_KSU_KERN 0x00000000 /* kernel mode */ 149 150 /* interrupt mask bits */ 151 #define SR_SINT0 0x00000100 /* enable s/w interrupt 0 */ 152 #define SR_SINT1 0x00000200 /* enable s/w interrupt 1 */ 153 #define SR_HINT0 0x00000400 /* enable h/w interrupt 1 */ 154 #define SR_HINT1 0x00000800 /* enable h/w interrupt 2 */ 155 #define SR_HINT2 0x00001000 /* enable h/w interrupt 3 */ 156 #define SR_HINT3 0x00002000 /* enable h/w interrupt 4 */ 157 #define SR_HINT4 0x00004000 /* enable h/w interrupt 5 */ 158 #define SR_HINT5 0x00008000 /* enable h/w interrupt 6 */ 159 160 /* alternative interrupt mask naming */ 161 #define SR_IM0 0x00000100 162 #define SR_IM1 0x00000200 163 #define SR_IM2 0x00000400 164 #define SR_IM3 0x00000800 165 #define SR_IM4 0x00001000 166 #define SR_IM5 0x00002000 167 #define SR_IM6 0x00004000 168 #define SR_IM7 0x00008000 169 170 #define SR_IMASK 0x0000ff00 171 172 #define SR_NMI 0x00080000 /* NMI occurred */ 173 #define SR_SR 0x00100000 /* soft reset occurred */ 174 #define SR_TS 0x00200000 /* TLB shutdown */ 175 #define SR_BEV 0x00400000 /* boot exception vectors */ 176 #define SR_PX 0x00800000 /* user 64-bit reg / 32-bit addr */ 177 #define SR_MX 0x01000000 /* enable MDMX/DSP ASE */ 178 #define SR_RE 0x02000000 /* reverse endian (user mode) */ 179 #define SR_FR 0x04000000 /* 64-bit fpu registers */ 180 #define SR_RP 0x08000000 /* reduce power */ 181 182 #define SR_CU0 0x10000000 /* coprocessor 0 enable */ 183 #define SR_CU1 0x20000000 /* coprocessor 1 enable */ 184 #define SR_CU2 0x40000000 /* coprocessor 2 enable */ 185 #define SR_CU3 0x80000000 /* coprocessor 3 enable */ 186 187 188 /* 189 * MIPS32r2 HWREna Register (CP0 Register 7, Select 0) 190 */ 191 #define HWRENA_CPUNUM 0x00000001 192 #define HWRENA_SYNCSTEP 0x00000002 193 #define HWRENA_CC 0x00000004 194 #define HWRENA_CCRES 0x00000008 195 196 /* 197 * MIPS32r2 IntCtl Register (CP0 Register 12, Select 1) 198 */ 199 #define INTCTL_IPTI 0xe0000000 /* timer i/u pending bit */ 200 #define INTCTL_IPTI_SHIFT 29 201 #define INTCTL_IPPCI 0x1c000000 /* perfctr i/u pending bit */ 202 #define INTCTL_IPPCI_SHIFT 26 203 #define INTCTL_VS 0x000003e0 /* vector spacing */ 204 #define INTCTL_VS_0 (0x00<<5) 205 #define INTCTL_VS_32 (0x01<<5) 206 #define INTCTL_VS_64 (0x02<<5) 207 #define INTCTL_VS_128 (0x04<<5) 208 #define INTCTL_VS_256 (0x08<<5) 209 #define INTCTL_VS_512 (0x10<<5) 210 211 /* 212 * MIPS32r2 SRSCtl Register (CP0 Register 12, Select 2) 213 */ 214 #define SRSCTL_HSS 0x3c000000 /* highest shadow set */ 215 #define SRSCTL_HSS_SHIFT 26 216 #define SRSCTL_EICSS 0x003c0000 /* EIC shadow set */ 217 #define SRSCTL_EICSS_SHIFT 18 218 #define SRSCTL_ESS 0x0000f000 /* exception shadow set */ 219 #define SRSCTL_ESS_SHIFT 12 220 #define SRSCTL_PSS 0x000003c0 /* previous shadow set */ 221 #define SRSCTL_PSS_SHIFT 6 222 #define SRSCTL_CSS 0x0000000f /* current shadow set */ 223 #define SRSCTL_CSS_SHIFT 0 224 225 /* 226 * MIPS32 Config0 Register (CP0 Register 16, Select 0) 227 */ 228 #define CFG0_M 0x80000000 /* Config1 implemented */ 229 #define CFG0_BE 0x00008000 /* Big Endian */ 230 #define CFG0_ATMASK 0x00006000 /* Architecture type: */ 231 #define CFG0_AT_M32 (0<<13) /* MIPS32 */ 232 #define CFG0_AT_M64_A32 (1<<13) /* MIPS64, 32-bit addresses */ 233 #define CFG0_AT_M64_A64 (2<<13) /* MIPS64, 64-bit addresses */ 234 #define CFG0_AT_RES (3<<13) 235 #define CFG0_ARMASK 0x00001c00 236 #define CFG0_ARSHIFT 10 237 #define CFG0_MTMASK 0x00000380 238 #define CFG0_MT_NONE (0<<7) 239 #define CFG0_MT_TLB (1<<7) 240 #define CFG0_MT_BAT (2<<7) 241 #define CFG0_MT_NONSTD (3<<7) 242 #define CFG0_VI 0x00000008 /* Icache is virtual */ 243 #define CFG0_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ 244 245 /* 246 * R4000 compatibility Config Register (actually processor dependent) 247 */ 248 #define CFG_BE CFG0_BE /* Big Endian */ 249 #define CFG_K0MASK CFG0_K0MASK /* KSEG0 coherency algorithm */ 250 251 /* 252 * MIPS32 Config1 Register (CP0 Register 16, Select 1) 253 */ 254 #define CFG1_M 0x80000000 /* Config2 implemented */ 255 #define CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */ 256 #define CFG1_MMUSSHIFT 25 257 #define CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */ 258 #define CFG1_ISSHIFT 22 259 #define CFG1_ILMASK 0x00380000 /* icache line size 2<<n */ 260 #define CFG1_ILSHIFT 19 261 #define CFG1_IAMASK 0x00070000 /* icache ways - 1 */ 262 #define CFG1_IASHIFT 16 263 #define CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */ 264 #define CFG1_DSSHIFT 13 265 #define CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */ 266 #define CFG1_DLSHIFT 10 267 #define CFG1_DAMASK 0x00000380 /* dcache ways - 1 */ 268 #define CFG1_DASHIFT 7 269 #define CFG1_C2 0x00000040 /* Coprocessor 2 present */ 270 #define CFG1_MD 0x00000020 /* MDMX implemented */ 271 #define CFG1_PC 0x00000010 /* performance counters implemented */ 272 #define CFG1_WR 0x00000008 /* watch registers implemented */ 273 #define CFG1_CA 0x00000004 /* compression (mips16) implemented */ 274 #define CFG1_EP 0x00000002 /* ejtag implemented */ 275 #define CFG1_FP 0x00000001 /* fpu implemented */ 276 277 278 /* 279 * MIPS32r2 Config2 Register (CP0 Register 16, Select 2) 280 */ 281 #define CFG2_M 0x80000000 /* Config3 implemented */ 282 #define CFG2_TUMASK 0x70000000 /* tertiary cache control */ 283 #define CFG2_TUSHIFT 28 284 #define CFG2_TSMASK 0x0f000000 /* tcache sets per wway 64<<n */ 285 #define CFG2_TSSHIFT 24 286 #define CFG2_TLMASK 0x00f00000 /* tcache line size 2<<n */ 287 #define CFG2_TLSHIFT 20 288 #define CFG2_TAMASK 0x000f0000 /* tcache ways - 1 */ 289 #define CFG2_TASHIFT 16 290 #define CFG2_SUMASK 0x0000f000 /* secondary cache control */ 291 #define CFG2_SUSHIFT 12 292 #define CFG2_SSMASK 0x00000f00 /* scache sets per wway 64<<n */ 293 #define CFG2_SSSHIFT 8 294 #define CFG2_SLMASK 0x000000f0 /* scache line size 2<<n */ 295 #define CFG2_SLSHIFT 4 296 #define CFG2_SAMASK 0x0000000f /* scache ways - 1 */ 297 #define CFG2_SASHIFT 0 298 299 /* 300 * MIPS32r2 Config3 Register (CP0 Register 16, Select 3) 301 */ 302 #define CFG3_M 0x80000000 /* Config4 implemented */ 303 #define CFG3_ISAONEXC 0x00010000 /* ISA mode on exception entry */ 304 #define CFG3_DSPP 0x00000400 /* DSP ASE present */ 305 #define CFG3_LPA 0x00000080 /* Large physical addresses */ 306 #define CFG3_VEIC 0x00000040 /* Vectored external i/u controller */ 307 #define CFG3_VI 0x00000020 /* Vectored i/us */ 308 #define CFG3_SP 0x00000010 /* Small page support */ 309 #define CFG3_MT 0x00000004 /* MT ASE present */ 310 #define CFG3_SM 0x00000002 /* SmartMIPS ASE */ 311 #define CFG3_TL 0x00000001 /* Trace Logic */ 312 313 314 /* 315 * Primary cache mode 316 */ 317 #define CFG_C_UNCACHED 2 318 #define CFG_C_WBACK 3 319 #define CFG_C_NONCOHERENT 3 320 321 #if 0 322 /* These cache modes are CPU specific */ 323 #define CFG_C_WTHRU_NOALLOC 0 324 #define CFG_C_WTHRU_ALLOC 1 325 #define CFG_C_COHERENTXCL 4 326 #define CFG_C_COHERENTXCLW 5 327 #define CFG_C_COHERENTUPD 6 328 #define CFG_C_UNCACHED_ACCEL 7 329 #endif 330 331 332 /* 333 * Primary Cache TagLo (CP0 Register 28, Select 0/2) 334 */ 335 #define TAG_PTAG_MASK 0xffffff00 /* Primary Tag */ 336 #define TAG_PTAG_SHIFT 8 337 #define TAG_PSTATE_MASK 0x000000c0 /* Primary Cache State */ 338 #define TAG_PSTATE_SHIFT 6 339 #define TAG_PSTATE_LOCK 0x00000020 340 #define TAG_PARITY_MASK 0x00000001 /* Primary Tag Parity */ 341 #define TAG_PARITY_SHIFT 0 342 343 /* primary cache state (XXX actually implementation specific) */ 344 #define PSTATE_INVAL 0 345 #define PSTATE_SHARED 1 346 #define PSTATE_CLEAN_EXCL 2 347 #define PSTATE_DIRTY_EXCL 3 348 349 350 /* 351 * Cache operations 352 */ 353 #define Index_Invalidate_I 0x00 /* 0 0 */ 354 #define Index_Writeback_Inv_D 0x01 /* 0 1 */ 355 #define Index_Writeback_Inv_T 0x02 /* 0 2 */ 356 #define Index_Writeback_Inv_S 0x03 /* 0 3 */ 357 #define Index_Load_Tag_I 0x04 /* 1 0 */ 358 #define Index_Load_Tag_D 0x05 /* 1 1 */ 359 #define Index_Load_Tag_T 0x06 /* 1 2 */ 360 #define Index_Load_Tag_S 0x07 /* 1 3 */ 361 #define Index_Store_Tag_I 0x08 /* 2 0 */ 362 #define Index_Store_Tag_D 0x09 /* 2 1 */ 363 #define Index_Store_Tag_T 0x0A /* 2 2 */ 364 #define Index_Store_Tag_S 0x0B /* 2 3 */ 365 #define Hit_Invalidate_I 0x10 /* 4 0 */ 366 #define Hit_Invalidate_D 0x11 /* 4 1 */ 367 #define Hit_Invalidate_T 0x12 /* 4 2 */ 368 #define Hit_Invalidate_S 0x13 /* 4 3 */ 369 #define Fill_I 0x14 /* 5 0 */ 370 #define Hit_Writeback_Inv_D 0x15 /* 5 1 */ 371 #define Hit_Writeback_Inv_T 0x16 /* 5 2 */ 372 #define Hit_Writeback_Inv_S 0x17 /* 5 3 */ 373 #define Hit_Writeback_D 0x19 /* 6 1 */ 374 #define Hit_Writeback_T 0x1A /* 6 1 */ 375 #define Hit_Writeback_S 0x1B /* 6 3 */ 376 #define Fetch_Lock_I 0x1C /* 7 0 */ 377 #define Fetch_Lock_D 0x1D /* 7 1 */ 378 379 /* MIPS32 WatchLo Register (CP0 Register 18) */ 380 #define WATCHLO_VA 0xfffffff8 381 #define WATCHLO_I 0x00000004 382 #define WATCHLO_R 0x00000002 383 #define WATCHLO_W 0x00000001 384 385 /* MIPS32 WatchHi Register (CP0 Register 19) */ 386 #define WATCHHI_M 0x80000000 387 #define WATCHHI_G 0x40000000 388 #define WATCHHI_ASIDMASK 0x00ff0000 389 #define WATCHHI_ASIDSHIFT 16 390 #define WATCHHI_MASK 0x00000ffc 391 #define WATCHHI_I 0x00000004 392 #define WATCHHI_R 0x00000002 393 #define WATCHHI_W 0x00000001 394 395 /* MIPS32 PerfCnt Register (CP0 Register 25) */ 396 #define PERFCNT_M 0x80000000 397 #define PERFCNT_EVENTMASK 0x000007e0 398 #define PERFCNT_EVENTSHFT 5 399 #define PERFCNT_IE 0x00000010 400 #define PERFCNT_U 0x00000008 401 #define PERFCNT_S 0x00000004 402 #define PERFCNT_K 0x00000002 403 #define PERFCNT_EXL 0x00000001 404 405 /* MIPS32r2 PageGrain Register (CP0 Register 5, Select 1) */ 406 #define PAGEGRAIN_ELPA 0x20000000 /* Enable large phusical addresses */ 407 #define PAGEGRAIN_ESP 0x10000000 /* Enable small (1KB) page support */ 408 409 /* MIPS32r2 EBase Register (CP0 Register 15, Select 1) */ 410 #define EBASE_BASE 0xfffff000 /* Exception base */ 411 #define EBASE_CPU 0x000003ff /* CPU number */ 412 413 #ifdef __ASSEMBLER__ 414 415 /* 416 * MIPS32 Coprocessor 0 register numbers 417 */ 418 #define C0_INDEX $0 419 #define C0_INX $0 420 #define C0_RANDOM $1 421 #define C0_RAND $1 422 #define C0_ENTRYLO0 $2 423 #define C0_TLBLO0 $2 424 #define C0_ENTRYLO1 $3 425 #define C0_TLBLO1 $3 426 #define C0_CONTEXT $4 427 #define C0_CTXT $4 428 #define C0_PAGEMASK $5 429 #define C0_PAGEGRAIN $5,1 430 #define C0_WIRED $6 431 #define C0_HWRENA $7 432 #define C0_BADVADDR $8 433 #define C0_VADDR $8 434 #define C0_COUNT $9 435 #define C0_ENTRYHI $10 436 #define C0_TLBHI $10 437 #define C0_COMPARE $11 438 #define C0_STATUS $12 439 #define C0_SR $12 440 #define C0_INTCTL $12,1 441 #define C0_SRSCTL $12,2 442 #define C0_SRSMAP $12,3 443 #define C0_CAUSE $13 444 #define C0_CR $13 445 #define C0_EPC $14 446 #define C0_PRID $15 447 #define C0_EBASE $15,1 448 #define C0_CONFIG $16 449 #define C0_CONFIG0 $16,0 450 #define C0_CONFIG1 $16,1 451 #define C0_CONFIG2 $16,2 452 #define C0_CONFIG3 $16,3 453 #define C0_LLADDR $17 454 #define C0_WATCHLO $18 455 #define C0_WATCHHI $19 456 #define C0_DEBUG $23 457 #define C0_DEPC $24 458 #define C0_PERFCNT $25 459 #define C0_ERRCTL $26 460 #define C0_CACHEERR $27 461 #define C0_TAGLO $28 462 #define C0_ITAGLO $28 463 #define C0_DTAGLO $28,2 464 #define C0_TAGLO2 $28,4 465 #define C0_DATALO $28,1 466 #define C0_IDATALO $28,1 467 #define C0_DDATALO $28,3 468 #define C0_DATALO2 $28,5 469 #define C0_TAGHI $29 470 #define C0_DATAHI $29,1 471 #define C0_ERRPC $30 472 #define C0_DESAVE $31 473 474 $index = $0 475 $random = $1 476 $entrylo0 = $2 477 $entrylo1 = $3 478 $context = $4 479 $pagemask = $5 480 $wired = $6 481 $hwrena = $7 482 $vaddr = $8 483 $badvaddr = $8 484 $count = $9 485 $entryhi = $10 486 $compare = $11 487 $sr = $12 488 $cr = $13 489 $epc = $14 490 $prid = $15 491 $config = $16 492 $lladdr = $17 493 $watchlo = $18 494 $watchhi = $19 495 $debug = $23 496 $depc = $24 497 $perfcnt = $25 498 $errctl = $26 499 $cacheerr = $27 500 $taglo = $28 501 $taghi = $29 502 $errpc = $30 503 $desave = $31 504 505 506 #else /* !__ASSEMBLER__ */ 507 508 /* 509 * Standard types 510 */ 511 typedef unsigned long reg32_t; /* a 32-bit register */ 512 typedef unsigned long long reg64_t; /* a 64-bit register */ 513 #if __mips == 64 || __mips64 514 typedef unsigned long long reg_t; 515 typedef signed long long sreg_t; 516 #else 517 typedef unsigned long reg_t; 518 typedef signed long sreg_t; 519 #endif 520 521 /* 522 * MIPS32 Coprocessor 0 register numbers 523 */ 524 #define C0_INDEX 0 525 #define C0_INX 0 526 #define C0_RANDOM 1 527 #define C0_RAND 1 528 #define C0_ENTRYLO0 2 529 #define C0_TLBLO0 2 530 #define C0_ENTRYLO1 3 531 #define C0_TLBLO1 3 532 #define C0_CONTEXT 4 533 #define C0_CTXT 4 534 #define C0_PAGEMASK 5 535 #define C0_WIRED 6 536 #define C0_HWRENA 7 537 #define C0_BADVADDR 8 538 #define C0_VADDR 8 539 #define C0_COUNT 9 540 #define C0_ENTRYHI 10 541 #define C0_TLBHI 10 542 #define C0_COMPARE 11 543 #define C0_STATUS 12 544 #define C0_SR 12 545 #define C0_CAUSE 13 546 #define C0_CR 13 547 #define C0_EPC 14 548 #define C0_PRID 15 549 #define C0_CONFIG 16 550 #define C0_LLADDR 17 551 #define C0_WATCHLO 18 552 #define C0_WATCHHI 19 553 #define C0_DEBUG 23 554 #define C0_DEPC 24 555 #define C0_PERFCNT 25 556 #define C0_ERRCTL 26 557 #define C0_CACHEERR 27 558 #define C0_TAGLO 28 559 #define C0_TAGHI 29 560 #define C0_ERRPC 30 561 #define C0_DESAVE 31 562 563 #define _mips_nop() \ 564 __asm__ __volatile ("%(ssnop%)" : :) 565 566 #if ! __mips16 || __force_mips16_asm 567 # define _mips_sync() __asm__ __volatile__ ("sync" : : : "memory") 568 #else 569 extern void _mips_sync(void); 570 #endif 571 572 /* wait for unmasked interrupt */ 573 #define _mips_wait() \ 574 __asm__ __volatile ("wait") 575 576 /* 577 * Define macros for accessing the MIPS32 coprocessor 0 registers. 578 * Most apart from "set" return the original register value. 579 */ 580 581 #if ! __mips16 || __force_mips16_asm 582 583 #define _m32c0_mfc0(reg, sel) \ 584 __extension__ ({ \ 585 register unsigned long __r; \ 586 __asm__ __volatile ("mfc0 %0,$%1,%2" \ 587 : "=d" (__r) \ 588 : "JK" (reg), "JK" (sel)); \ 589 __r; \ 590 }) 591 592 #if __mips_isa_rev >= 2 593 #define _m32c0_mtc0(reg, sel, val) \ 594 do { \ 595 __asm__ __volatile ("%(mtc0 %z0,$%1,%2; ehb%)" \ 596 : \ 597 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \ 598 : "memory"); \ 599 } while (0) 600 #else 601 #define _m32c0_mtc0(reg, sel, val) \ 602 do { \ 603 __asm__ __volatile ("%(mtc0 %z0,$%1,%2; ssnop; ssnop; ehb%)" \ 604 : \ 605 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \ 606 : "memory"); \ 607 } while (0) 608 #endif 609 610 #define _m32c0_mxc0(reg, sel, val) \ 611 __extension__ ({ \ 612 register reg32_t __o; \ 613 __o = _m32c0_mfc0 (reg, sel); \ 614 _m32c0_mtc0 (reg, sel, val); \ 615 __o; \ 616 }) 617 618 #else 619 620 #define _m32c0_mfc0(rn, sel) _mips_xxc0 ((rn) + (sel)*32, 0, 0) 621 #define _m32c0_mtc0(rn, sel, v) (void) _mips_xxc0 ((rn) + (sel)*32, ~0, v) 622 #define _m32c0_mxc0(rn, sel, v) _mips_xxc0 ((rn) + (sel)*32, ~0, v) 623 624 #endif /* !__mips16 */ 625 626 /* generic equivalents for mips/cpu.h */ 627 #define _mips_mfc0(r) _m32c0_mfc0(r,0) 628 #define _mips_mtc0(r,v) _m32c0_mtc0(r,0,v) 629 630 /* MIPS32 Config0 register */ 631 #define mips32_getconfig0() _mips_mfc0(C0_CONFIG) 632 #define mips32_setconfig0(v) _mips_mtc0(C0_CONFIG,v) 633 #define mips32_xchconfig0(v) _mips_mxc0(C0_CONFIG,v) 634 #define mips32_bicconfig0(clr) _mips_bcc0(C0_CONFIG,clr) 635 #define mips32_bisconfig0(set) _mips_bsc0(C0_CONFIG,set) 636 #define mips32_bcsconfig0(c,s) _mips_bcsc0(C0_CONFIG,c,s) 637 638 /* MIPS32 Config1, 2 & 3 register */ 639 #define mips32_getconfig1() _m32c0_mfc0(C0_CONFIG,1) 640 #define mips32_getconfig2() _m32c0_mfc0(C0_CONFIG,2) 641 #define mips32_getconfig3() _m32c0_mfc0(C0_CONFIG,3) 642 643 /* MIPS32 WatchLo register */ 644 #define mips32_getwatchlo(sel) _mips_xxc0(C0_WATCHLO + (sel)*32, 0, 0) 645 #define mips32_setwatchlo(sel,v) _mips_xxc0(C0_WATCHLO + (sel)*32, ~0, v) 646 647 /* MIPS32 WatchHi register */ 648 #define mips32_getwatchhi(sel) _mips_xxc0(C0_WATCHHI + (sel)*32, 0, 0) 649 #define mips32_setwatchhi(sel,v) _mips_xxc0(C0_WATCHHI + (sel)*32, ~0, v) 650 651 /* MIPS32 Debug register */ 652 #define mips32_getdebug() _mips_mfc0(C0_DEBUG) 653 #define mips32_setdebug(v) _mips_mtc0(C0_DEBUG,v) 654 #define mips32_xchdebug(v) _mips_mxc0(C0_DEBUG,v) 655 #define mips32_bicdebug(clr) _mips_bcc0(C0_DEBUG,clr) 656 #define mips32_bisdebug(set) _mips_bsc0(C0_DEBUG,set) 657 #define mips32_bcsdebug(c,s) _mips_bcsc0(C0_DEBUG,c,s) 658 659 /* MIPS32 ErrCtl register */ 660 #define mips32_geterrctl() _mips_mfc0(C0_ERRCTL) 661 #define mips32_seterrctl(x) _mips_mtc0(C0_ERRCTL,x) 662 #define mips32_xcherrctl(x) _mips_mxc0(C0_ERRCTL,x) 663 #define mips32_bicerrctl(clr) _mips_bcc0(C0_ERRCTL,clr) 664 #define mips32_biserrctl(set) _mips_bsc0(C0_ERRCTL,set) 665 #define mips32_bcserrctl(c,s) _mips_bcsc0(C0_ERRCTL,c,s) 666 667 /* MIPS32 TagLo register */ 668 #define mips32_getitaglo() _mips_mfc0(C0_TAGLO) /* alias define */ 669 #define mips32_setitaglo(x) _mips_mtc0(C0_TAGLO,x) /* alias define */ 670 #define mips32_xchitaglo(x) _mips_mxc0(C0_TAGLO,x) /* alias define */ 671 #define mips32_getdtaglo() _m32c0_mfc0(C0_TAGLO,2) 672 #define mips32_setdtaglo(x) _m32c0_mtc0(C0_TAGLO,2,x) 673 #define mips32_xchdtaglo(x) _m32c0_mxc0(C0_TAGLO,2,x) 674 #define mips32_gettaglo2() _m32c0_mfc0(C0_TAGLO,4) 675 #define mips32_settaglo2(x) _m32c0_mtc0(C0_TAGLO,4,x) 676 #define mips32_xchtaglo2(x) _m32c0_mxc0(C0_TAGLO,4,x) 677 678 /* MIPS32 DataLo register */ 679 #define mips32_getdatalo() _m32c0_mfc0(C0_TAGLO,1) 680 #define mips32_setdatalo(x) _m32c0_mtc0(C0_TAGLO,1,x) 681 #define mips32_xchdatalo(x) _m32c0_mxc0(C0_TAGLO,1,x) 682 #define mips32_getidatalo() mips32_getdatalo() /* alias define */ 683 #define mips32_setidatalo(x) mips32_setdatalo(x) /* alias define */ 684 #define mips32_xchidatalo(x) mips32_xchdatalo(x) /* alias define */ 685 #define mips32_getddatalo() _m32c0_mfc0(C0_TAGLO,3) 686 #define mips32_setddatalo(x) _m32c0_mtc0(C0_TAGLO,3,x) 687 #define mips32_xchddatalo(x) _m32c0_mxc0(C0_TAGLO,3,x) 688 #define mips32_getdatalo2() _m32c0_mfc0(C0_TAGLO,5) 689 #define mips32_setdatalo2(x) _m32c0_mtc0(C0_TAGLO,5,x) 690 #define mips32_xchdatalo2(x) _m32c0_mxc0(C0_TAGLO,5,x) 691 692 /* MIPS32r2 IntCtl register */ 693 #define mips32_getintctl() _m32c0_mfc0(12,1) 694 #define mips32_setintctl(x) _m32c0_mtc0(12,1,x) 695 #define mips32_xchintctl(x) _m32c0_mxc0(12,1,x) 696 697 /* MIPS32r2 SRSCtl register */ 698 #define mips32_getsrsctl() _m32c0_mfc0(12,2) 699 #define mips32_setsrsctl(x) _m32c0_mtc0(12,2,x) 700 #define mips32_xchsrsctl(x) _m32c0_mxc0(12,2,x) 701 702 /* MIPS32r2 SRSMap register */ 703 #define mips32_getsrsmapl() _m32c0_mfc0(12,3) 704 #define mips32_setsrsmap(x) _m32c0_mtc0(12,3,x) 705 #define mips32_xchsrsmap(x) _m32c0_mxc0(12,3,x) 706 707 /* MIPS32r2/SmartMIPS PageGrain register */ 708 #define mips32_getpagegrain() _m32c0_mfc0(5,1) 709 #define mips32_setpagegrain(x) _m32c0_mtc0(5,1,x) 710 #define mips32_xchpagegrain(x) _m32c0_mxc0(5,1,x) 711 712 /* MIPS32r2 HWREna register */ 713 #define mips32_gethwrena() _mips_mfc0(C0_HWRENA) 714 #define mips32_sethwrena(v) _mips_mtc0(C0_HWRENA,v) 715 #define mips32_xchhwrena(v) _mips_mxc0(C0_HWRENA,v) 716 #define mips32_bichwrena(clr) _mips_bcc0(C0_HWRENA,clr) 717 #define mips32_bishwrena(set) _mips_bsc0(C0_HWRENA,set) 718 #define mips32_bcshwrena(c,s) _mips_bcsc0(C0_HWRENA,c,s) 719 720 /* MIPS32r2 EBase register */ 721 #define mips32_getebase() _m32c0_mfc0(15,1) 722 #define mips32_setebase(x) _m32c0_mtc0(15,1,x) 723 #define mips32_xchebase(x) _m32c0_mxc0(15,1,x) 724 725 /* Define MIPS64 user-level intrinsics */ 726 #include "mips/mips32.h" 727 728 /* CP0 intrinsics */ 729 #if __mips_isa_rev >= 2 && (! __mips16 || __force_mips16_asm) 730 731 /* MIPS32r2 atomic interrupt disable */ 732 #define _mips_intdisable() __extension__({ \ 733 unsigned int __v; \ 734 __asm__ __volatile__ ("di %0; ehb" : "=d" (__v)); \ 735 __v; \ 736 }) 737 738 /* MIPS32r2 atomic interrupt restore */ 739 #define _mips_intrestore(x) \ 740 mips_setsr (x) 741 742 /* MIPS32r2 set SRSCtl.PSS (previous shadow set), returning old value */ 743 extern unsigned int _mips32r2_xchsrspss (unsigned int); 744 745 #if 0 746 /* simpler to make this a function in mipscp0.sx */ 747 #define _mips32r2_xchsrspss(set) \ 748 __extension__({ \ 749 unsigned int __tmp, __old; \ 750 __asm __volatile ("mfc0 %0,$12,2\n\ 751 ext %1,%0,6,4\n\ 752 ins %0,%z2,6,4\n\ 753 mtc0 %0,$12,2\n\ 754 la %0,1f\n\ 755 jr.hb %0\n\ 756 1:" 757 : "=&d" (__tmp), "=&d" (__old) \ 758 : "dJ" (set)); \ 759 __old; \ 760 }) 761 #endif 762 763 /* MIPS32r2 write previous gpr */ 764 #define _mips32r2_wrpgpr(regno, val) \ 765 do { \ 766 __asm __volatile ("wrpgpr $%0,%z1" \ 767 : /* no outputs */ \ 768 : "JK" (regno), "dJ" (val)); \ 769 } while (0) 770 771 /* MIPS32r2 read previous gpr */ 772 #define _mips32r2_rdpgpr(regno) \ 773 __extension__({ \ 774 reg_t __val; \ 775 __asm __volatile ("rdpgpr %0,$%1" \ 776 : "=d" (__val) \ 777 : "JK" (regno)); \ 778 __val; \ 779 }) 780 781 #endif /* __mips_isa_rev >= 2 && ! __mips16 */ 782 783 #endif /* __ASSEMBLER__ */ 784 785 /* MIPS32 PREF instruction hint codes */ 786 #define PREF_LOAD 0 787 #define PREF_STORE 1 788 #define PREF_LOAD_STREAMED 4 789 #define PREF_STORE_STREAMED 5 790 #define PREF_LOAD_RETAINED 6 791 #define PREF_STORE_RETAINED 7 792 #define PREF_WRITEBACK_INVAL 25 793 #define PREF_PREPAREFORSTORE 30 794 795 #ifdef __cplusplus 796 } 797 #endif 798 #endif /* _M32C0_H_ */ 799
