1 // ------------------------------------------------------------
2 // v7-A Cache, TLB and Branch Prediction Maintenance Operations
3 // Header File
4 //
5 // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved.
6 // Use, modification and redistribution of this file is subject to your possession of a
7 // valid End User License Agreement for the Arm Product of which these examples are part of
8 // and your compliance with all applicable terms and conditions of such licence agreement.
9 // ------------------------------------------------------------
10 
11 #ifndef _ARMV7A_GENERIC_H
12 #define _ARMV7A_GENERIC_H
13 
14 // ------------------------------------------------------------
15 // Memory barrier mnemonics
16 enum MemBarOpt {
17   RESERVED_0  = 0,  RESERVED_1 = 1, OSHST = 2, OSH = 3,
18   RESERVED_4  = 4,  RESERVED_5 = 5, NSHST = 6, NSH = 7,
19   RESERVED_8  = 8,  RESERVED_9 = 9, ISHST = 10, ISH = 11,
20   RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15
21 };
22 
23 //
24 // Note:
25 // *_IS() stands for "inner shareable"
26 // DO NOT USE THESE FUNCTIONS ON A CORTEX-A8
27 //
28 
29 // ------------------------------------------------------------
30 // Interrupts
31 // Enable/disables IRQs (not FIQs)
32 void enableInterrupts(void);
33 void disableInterrupts(void);
34 
35 // ------------------------------------------------------------
36 // Caches
37 
38 void invalidateCaches_IS(void);
39 void cleanInvalidateDCache(void);
40 void invalidateCaches_IS(void);
41 void enableCaches(void);
42 void disableCaches(void);
43 void invalidateCaches(void);
44 void cleanDCache(void);
45 
46 // ------------------------------------------------------------
47 // TLBs
48 
49 void invalidateUnifiedTLB(void);
50 void invalidateUnifiedTLB_IS(void);
51 
52 // ------------------------------------------------------------
53 // Branch prediction
54 
55 void flushBranchTargetCache(void);
56 void flushBranchTargetCache_IS(void);
57 
58 // ------------------------------------------------------------
59 // High Vecs
60 
61 void enableHighVecs(void);
62 void disableHighVecs(void);
63 
64 // ------------------------------------------------------------
65 // ID Registers
66 
67 unsigned int getMIDR(void);
68 
69 #define MIDR_IMPL_SHIFT  24
70 #define MIDR_IMPL_MASK   0xFF
71 #define MIDR_VAR_SHIFT   20
72 #define MIDR_VAR_MASK    0xF
73 #define MIDR_ARCH_SHIFT  16
74 #define MIDR_ARCH_MASK   0xF
75 #define MIDR_PART_SHIFT  4
76 #define MIDR_PART_MASK   0xFFF
77 #define MIDR_REV_SHIFT   0
78 #define MIDR_REV_MASK    0xF
79 
80 // tmp = get_MIDR();
81 // implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
82 // variant     = (tmp >> MIDR_VAR_SHIFT)  & MIDR_VAR_MASK;
83 // architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK;
84 // part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK;
85 // revision    = tmp & MIDR_REV_MASK;
86 
87 #define MIDR_PART_CA5    0xC05
88 #define MIDR_PART_CA8    0xC08
89 #define MIDR_PART_CA9    0xC09
90 
91 unsigned int getMPIDR(void);
92 
93 #define MPIDR_FORMAT_SHIFT  31
94 #define MPIDR_FORMAT_MASK   0x1
95 #define MPIDR_UBIT_SHIFT    30
96 #define MPIDR_UBIT_MASK     0x1
97 #define MPIDR_CLUSTER_SHIFT 7
98 #define MPIDR_CLUSTER_MASK  0xF
99 #define MPIDR_CPUID_SHIFT   0
100 #define MPIDR_CPUID_MASK    0x3
101 
102 #define MPIDR_CPUID_CPU0    0x0
103 #define MPIDR_CPUID_CPU1    0x1
104 #define MPIDR_CPUID_CPU2    0x2
105 #define MPIDR_CPUID_CPU3    0x3
106 
107 #define MPIDR_UNIPROCESSPR  0x1
108 
109 #define MPDIR_NEW_FORMAT    0x1
110 
111 // ------------------------------------------------------------
112 // Context ID
113 
114 unsigned int getContextID(void);
115 
116 void setContextID(unsigned int);
117 
118 #define CONTEXTID_ASID_SHIFT   0
119 #define CONTEXTID_ASID_MASK    0xFF
120 #define CONTEXTID_PROCID_SHIFT 8
121 #define CONTEXTID_PROCID_MASK  0x00FFFFFF
122 
123 // tmp    = getContextID();
124 // ASID   = tmp & CONTEXTID_ASID_MASK;
125 // PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK;
126 
127 // ------------------------------------------------------------
128 // SMP related for Armv7-A MPCore processors
129 //
130 // DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8
131 
132 // Returns the base address of the private peripheral memory space
133 unsigned int getBaseAddr(void);
134 
135 // Returns the CPU ID (0 to 3) of the CPU executed on
136 #define MP_CPU0   (0)
137 #define MP_CPU1   (1)
138 #define MP_CPU2   (2)
139 #define MP_CPU3   (3)
140 unsigned int getCPUID(void);
141 
142 // Set this core as participating in SMP
143 void joinSMP(void);
144 
145 // Set this core as NOT participating in SMP
146 void leaveSMP(void);
147 
148 // Go to sleep, never returns
149 void goToSleep(void);
150 
151 #endif
152 
153 // ------------------------------------------------------------
154 // End of v7.h
155 // ------------------------------------------------------------
156