1/***************************************************************************
2 * Copyright (c) 2024 Microsoft Corporation
3 *
4 * This program and the accompanying materials are made available under the
5 * terms of the MIT License which is available at
6 * https://opensource.org/licenses/MIT.
7 *
8 * SPDX-License-Identifier: MIT
9 **************************************************************************/
10
11/**************************************************************************/
12/*   Copyright (c) Cadence Design Systems, Inc.                           */
13/*                                                                        */
14/* Permission is hereby granted, free of charge, to any person obtaining  */
15/* a copy of this software and associated documentation files (the        */
16/* "Software"), to deal in the Software without restriction, including    */
17/* without limitation the rights to use, copy, modify, merge, publish,    */
18/* distribute, sublicense, and/or sell copies of the Software, and to     */
19/* permit persons to whom the Software is furnished to do so, subject to  */
20/* the following conditions:                                              */
21/*                                                                        */
22/* The above copyright notice and this permission notice shall be         */
23/* included in all copies or substantial portions of the Software.        */
24/*                                                                        */
25/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
26/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
27/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
28/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
29/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
30/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
31/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
32/**************************************************************************/
33
34/**************************************************************************/
35/**************************************************************************/
36/**                                                                       */
37/** ThreadX Component                                                     */
38/**                                                                       */
39/**   Thread                                                              */
40/**                                                                       */
41/**************************************************************************/
42/**************************************************************************/
43
44
45#include "xtensa_rtos.h"
46#include "tx_api_asm.h"
47
48    .text
49
50/**************************************************************************/
51/*                                                                        */
52/*  DESCRIPTION                                                           */
53/*                                                                        */
54/*    This function builds a stack frame on the supplied thread's stack.  */
55/*    The stack frame looks like an interrupt frame or a solicited frame  */
56/*    depending on the exception architecture of the target hardware.     */
57/*                                                                        */
58/*  RELEASE HISTORY                                                       */
59/*                                                                        */
60/*    DATE              NAME                      DESCRIPTION             */
61/*                                                                        */
62/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
63/*                                                                        */
64/**************************************************************************/
65
66//  VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
67//  {
68    .globl  _tx_thread_stack_build
69    .type   _tx_thread_stack_build,@function
70    .align  4
71_tx_thread_stack_build:
72
73    ENTRY0
74
75    /* Get logical base of stack area (top). */
76    l32i    a5, a2, tx_thread_stack_end /* get top-1 of stack area */
77    addi    a5, a5, 1                   /* undo the -1 */
78    srli    a5, a5, 4                   /* force 16-byte alignment */
79    slli    a5, a5, 4                   /* a5 = post-dispatch SP (frame top) */
80
81    /* Allocate space for the frame (frame size is already 16-byte aligned). */
82    addi    a4, a5, -XT_STK_FRMSZ       /* a4 = pre-dispatch SP (frame base) */
83
84    /* Set the thread's SP. */
85    s32i    a4, a2, tx_thread_stack_ptr
86
87#if !XCHAL_HAVE_XEA2
88    addi    a4, a4, XT_STK_XTRA_SZ      /* a4 = base of exception frame */
89#endif
90
91    /* Clear the entire frame. (XEA3: only exception frame) */
92    movi    a6, 0                       /* a6 = 0 */
93    mov     a7, a4                      /* a7 = ptr to current word */
941:  s32i    a6, a7, 0                   /* clear current word */
95    addi    a7, a7, 4                   /* point to next word */
96    bltu    a7, a5, 1b                  /* repeat until frame top */
97
98#if XCHAL_HAVE_XEA2
99    s32i    a5, a4, XT_STK_A1           /* save post-dispatch SP in frame */
100#endif
101
102    /* Indicate a solicited or interrupted stack frame. */
103#if XCHAL_HAVE_XEA2
104    movi    a7, 0                       /* interrupted */
105#else
106    movi    a7, 0                       /* solicited */
107#endif
108    s32i    a7, a2, tx_thread_solicited
109
110    /*
111    Terminate GDB backtrace in this thread at the "return function" by ensuring
112    it's A0 == 0. Since frame was cleared, don't need to do this explicitly.
113    s32i    a6, a4, XT_STK_A0
114    */
115
116    /* Set the return address to the return function. */
117    /* Start thread via user exception exit dispatcher (could use any). */
118#if XCHAL_HAVE_XEA2
119    movi    a5, _xt_user_exit
120    s32i    a5, a4, XT_STK_EXIT
121#else
122    movi    a5, 0
123    s32i    a5, a4, XT_STK_ATOMCTL
124#endif
125
126    s32i    a3, a4, XT_STK_PC
127
128    /*
129    Set thread's initial PS for C code, all int levels enabled.
130    XEA2: Since we dispatch via level 1 (_xt_user_exit), must set PS.EXCM,
131      which will be cleared by 'rfe' after the dispatcher, to prevent
132      interrupts happening when PS is restored during the exit dispatcher.
133    XEA3: nothing special, other than setting the thread stack type.
134    */
135#if XCHAL_HAVE_XEA2
136    #ifdef __XTENSA_CALL0_ABI__
137    movi    a6, PS_UM | PS_EXCM
138    #else
139    movi    a6, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1)  /* pretend 'call4' */
140    #endif
141#else
142    movi    a6, PS_STACK_FIRSTKER
143#endif
144    s32i    a6, a4, XT_STK_PS
145
146#if XCHAL_HAVE_XEA2
147    #ifdef XT_USE_SWPRI
148    /* Set the initial virtual priority mask value to all 1's */
149    movi    a3, -1
150    s32i    a3, a4, XT_STK_VPRI
151    #endif
152#endif
153
154    RET0
155
156//  }
157
158