1 2 /**************************************************************************/ 3 /* Copyright (c) Cadence Design Systems, Inc. */ 4 /* */ 5 /* Permission is hereby granted, free of charge, to any person obtaining */ 6 /* a copy of this software and associated documentation files (the */ 7 /* "Software"), to deal in the Software without restriction, including */ 8 /* without limitation the rights to use, copy, modify, merge, publish, */ 9 /* distribute, sublicense, and/or sell copies of the Software, and to */ 10 /* permit persons to whom the Software is furnished to do so, subject to */ 11 /* the following conditions: */ 12 /* */ 13 /* The above copyright notice and this permission notice shall be */ 14 /* included in all copies or substantial portions of the Software. */ 15 /* */ 16 /* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */ 17 /* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */ 18 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */ 19 /* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */ 20 /* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */ 21 /* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */ 22 /* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 /**************************************************************************/ 24 25 /************************************************************************** 26 XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY 27 28 This header contains timer related definitions and macros for use by 29 Xtensa RTOS source files. It includes and uses the Xtensa hardware 30 abstraction layer (HAL) to deal with config specifics. 31 32 If the RTOS has no timer interrupt, then there is no tick timer and the 33 clock frequency is irrelevant, so all of these macros are left undefined 34 and the Xtensa core configuration need not have a timer. 35 ***************************************************************************/ 36 37 #ifndef XTENSA_TIMER_H 38 #define XTENSA_TIMER_H 39 40 #include "xtensa_rtos.h" /* in case this wasn't included directly */ 41 42 #ifdef XT_RTOS_TIMER_INT /* skip all this stuff if no timer int */ 43 44 #ifdef __ASSEMBLER__ 45 #include <xtensa/coreasm.h> 46 #else 47 #include <xtensa/tie/xt_timer.h> 48 #endif 49 50 #include <xtensa/corebits.h> 51 #include <xtensa/config/system.h> 52 53 54 #if XCHAL_HAVE_XEA3 55 56 /* 57 If the user has not specified a timer by defining XT_TIMER_INDEX, then 58 select timer 0. 59 */ 60 #ifndef XT_TIMER_INDEX 61 #define XT_TIMER_INDEX 0 62 #endif 63 64 #else /* XEA2 */ 65 66 /* 67 Select timer to use for periodic tick, and determine its interrupt number 68 and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, 69 in which case its validity is checked (it must exist in this core and must 70 not be on a high priority interrupt - an error will be reported in invalid). 71 Otherwise select the first low or medium priority interrupt timer available. 72 */ 73 #ifndef XT_TIMER_INDEX 74 #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 75 #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL 76 #undef XT_TIMER_INDEX 77 #define XT_TIMER_INDEX 3 78 #endif 79 #endif 80 #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 81 #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL 82 #undef XT_TIMER_INDEX 83 #define XT_TIMER_INDEX 2 84 #endif 85 #endif 86 #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 87 #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL 88 #undef XT_TIMER_INDEX 89 #define XT_TIMER_INDEX 1 90 #endif 91 #endif 92 #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 93 #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL 94 #undef XT_TIMER_INDEX 95 #define XT_TIMER_INDEX 0 96 #endif 97 #endif 98 #endif 99 100 #endif /* XCHAL_HAVE_XEA3 */ 101 102 #ifndef XT_TIMER_INDEX 103 #error "There is no suitable timer in this Xtensa configuration." 104 #endif 105 106 #define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) 107 #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) 108 #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) 109 110 #if XCHAL_HAVE_XEA2 111 #define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) 112 #endif 113 114 #if XT_TIMER_INDEX == 0 115 #define XT_WSR_CCOMPARE XT_WSR_CCOMPARE0 116 #elif XT_TIMER_INDEX == 1 117 #define XT_WSR_CCOMPARE XT_WSR_CCOMPARE1 118 #elif XT_TIMER_INDEX == 2 119 #define XT_WSR_CCOMPARE XT_WSR_CCOMPARE2 120 #endif 121 122 #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED 123 #error "The timer selected by XT_TIMER_INDEX does not exist in this core." 124 #elif !XCHAL_HAVE_XEA3 && (XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL) 125 #error "The timer interrupt cannot be high priority (use medium or low)." 126 #endif 127 128 /* 129 Default number of timer ticks per second. This can be redefined as required 130 either by editing here or by overriding from the command line during build. 131 */ 132 #ifndef XT_TICK_PER_SEC 133 #define XT_TICK_PER_SEC 100 134 #endif 135 136 /* 137 Set processor clock frequency and determine clock divisor for timer tick. 138 If using a supported board via the board-independent API defined in xtbsp.h, 139 this may be left undefined but XT_BOARD must be defined. The frequency and 140 tick divisor will be computed during run-time initialization. 141 */ 142 #ifndef XT_BOARD 143 #ifndef XT_CLOCK_FREQ 144 #define XT_CLOCK_FREQ 1000000 145 #endif 146 #define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) 147 #else 148 #ifndef __ASSEMBLER__ 149 extern uint32_t xt_tick_divisor; 150 extern void xt_tick_divisor_init(void); 151 #endif 152 #define XT_TICK_DIVISOR xt_tick_divisor 153 #endif /* XT_BOARD */ 154 155 #endif /* XT_RTOS_TIMER_INT */ 156 #endif /* XTENSA_TIMER_H */ 157 158
