1;/*************************************************************************** 2; * Copyright (c) 2024 Microsoft Corporation 3; * 4; * This program and the accompanying materials are made available under the 5; * terms of the MIT License which is available at 6; * https://opensource.org/licenses/MIT. 7; * 8; * SPDX-License-Identifier: MIT 9; **************************************************************************/ 10; 11; 12;/**************************************************************************/ 13;/**************************************************************************/ 14;/** */ 15;/** ThreadX Component */ 16;/** */ 17;/** Thread */ 18;/** */ 19;/**************************************************************************/ 20;/**************************************************************************/ 21; 22; 23;#define TX_SOURCE_CODE 24; 25; 26;/* Include necessary system files. */ 27; 28;#include "tx_api.h" 29;#include "tx_thread.h" 30;#include "tx_timer.h" 31; 32; 33 .GLB __tx_thread_system_state 34 .GLB __tx_thread_current_ptr 35 .GLB __tx_thread_system_stack_ptr 36 .GLB __tx_thread_execute_ptr 37 .GLB __tx_timer_time_slice 38 .GLB __tx_thread_schedule 39 .GLB __tx_thread_preempt_disable 40; 41 .SECTION P,CODE 42;/**************************************************************************/ 43;/* */ 44;/* FUNCTION RELEASE */ 45;/* */ 46;/* _tx_thread_context_restore RXv2/CCRX */ 47;/* 6.1.11 */ 48;/* AUTHOR */ 49;/* */ 50;/* William E. Lamie, Microsoft Corporation */ 51;/* */ 52;/* DESCRIPTION */ 53;/* */ 54;/* This function restores the interrupt context if it is processing a */ 55;/* nested interrupt. If not, it returns to the interrupt thread if no */ 56;/* preemption is necessary. Otherwise, if preemption is necessary or */ 57;/* if no thread was running, the function returns to the scheduler. */ 58;/* */ 59;/* INPUT */ 60;/* */ 61;/* None */ 62;/* */ 63;/* OUTPUT */ 64;/* */ 65;/* None */ 66;/* */ 67;/* CALLS */ 68;/* */ 69;/* _tx_thread_schedule Thread scheduling routine */ 70;/* */ 71;/* CALLED BY */ 72;/* */ 73;/* ISRs Interrupt Service Routines */ 74;/* */ 75;/* RELEASE HISTORY */ 76;/* */ 77;/* DATE NAME DESCRIPTION */ 78;/* */ 79;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ 80;/* 10-15-2021 William E. Lamie Modified comment(s), and */ 81;/* removed unnecessary stack */ 82;/* type placement, */ 83;/* resulting in version 6.1.9 */ 84;/* 01-31-2022 William E. Lamie Modified comment(s), */ 85;/* resulting in version 6.1.10 */ 86;/* 04-25-2022 William E. Lamie Modified comment(s), */ 87;/* resulting in version 6.1.11 */ 88;/* */ 89;/**************************************************************************/ 90;VOID _tx_thread_context_restore(VOID) 91;{ 92 .GLB __tx_thread_context_restore 93__tx_thread_context_restore: 94; 95; /* Lockout interrupts. */ 96 97 CLRPSW I ; Disable interrupts 98 99; /* Determine if interrupts are nested. */ 100; if (--_tx_thread_system_state) 101; { 102 103 MOV.L #__tx_thread_system_state, R1 104 MOV.L [R1], R2 105 SUB #1, R2 106 MOV.L R2,[R1] 107 BEQ __tx_thread_not_nested_restore 108 109; 110; /* Interrupts are nested. */ 111; 112; /* Recover the saved registers from the interrupt stack 113; and return to the point of interrupt. */ 114; 115__tx_thread_nested_restore: 116 POPC FPSW ; Restore FPU status 117 POPM R14-R15 ; Restore R14-R15 118 POPM R3-R5 ; Restore R3-R5 119 POPM R1-R2 ; Restore R1-R2 120 RTE ; Return to point of interrupt, restore PSW including IPL 121; } 122 123__tx_thread_not_nested_restore: 124; 125; /* Determine if a thread was interrupted and no preemption is required. */ 126; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) 127; || (_tx_thread_preempt_disable)) 128; { 129 130 MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address 131 MOV.L [R1], R2 132 CMP #0, R2 133 BEQ __tx_thread_idle_system_restore 134 135 MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag 136 MOV.L [R3], R3 137 CMP #0, R3 138 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless 139 140 MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) 141 CMP [R3], R2 142 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring 143; 144__tx_thread_no_preempt_restore: 145 SETPSW U ; User stack 146 POPC FPSW ; Restore FPU status 147 POPM R14-R15 ; Restore R14-R15 148 POPM R3-R5 ; Restore R3-R5 149 POPM R1-R2 ; Restore R1-R2 150 RTE ; Return to point of interrupt, restore PSW including IPL 151 152; } 153; else 154; { 155 156__tx_thread_preempt_restore: 157 158; /* Save the remaining time-slice and disable it. */ 159; if (_tx_timer_time_slice) 160; { 161 162 MOV.L #__tx_timer_time_slice, R3 ; Pickup time-slice address 163 MOV.L [R3],R4 ; Pickup actual time-slice 164 CMP #0, R4 165 BEQ __tx_thread_dont_save_ts ; No time slice to save 166; 167; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; 168; _tx_timer_time_slice = 0; 169; 170 MOV.L R4,24[R2] ; Save thread's time slice 171 MOV.L #0,R4 ; Clear value 172 MOV.L R4,[R3] ; Disable global time slice flag 173; } 174__tx_thread_dont_save_ts: 175; 176; /* Now store the remaining registers! */ 177 178 SETPSW U ; User stack 179 PUSHM R6-R13 180 181 MVFACGU #0, A1, R4 ; Save accumulators. 182 MVFACHI #0, A1, R5 183 MVFACLO #0, A1, R6 184 PUSHM R4-R6 185 MVFACGU #0, A0, R4 186 MVFACHI #0, A0, R5 187 MVFACLO #0, A0, R6 188 PUSHM R4-R6 189 190; 191; /* Clear the current task pointer. */ 192; _tx_thread_current_ptr = TX_NULL; 193; R1 -> _tx_thread_current_ptr 194; R2 -> *_tx_thread_current_ptr 195 196 MOV.L R0,8[R2] ; Save thread's stack pointer in thread control block 197 MOV.L #0,R2 ; Build NULL value 198 MOV.L R2,[R1] ; Set current thread to NULL 199 200; /* Return to the scheduler. */ 201; _tx_thread_schedule(); 202 203__tx_thread_idle_system_restore: 204 MVTC #0, PSW ; Reset interrupt priority level to 0 205 BRA __tx_thread_schedule ; Jump to scheduler 206; } 207; 208;} 209; 210 .END 211
