1                     Microsoft's Azure RTOS ThreadX for Cortex-M33
2
3                              Using the AC6 Tools in Keil uVision
4
51. Import the ThreadX Projects
6
7In order to build the ThreadX library and the ThreadX demonstration, first open
8the AzureRTOS.uvmpw workspace (located in the "example_build" directory)
9into Keil.
10
11
122.  Building the ThreadX run-time Library
13
14Building the ThreadX library is easy; simply set the ThreadX_Library project
15as active, then then build the library. You should now observe the compilation
16and assembly of the ThreadX library. This project build produces the ThreadX
17library file ThreadX_Library.lib.
18Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
19replace the common files of the same name.
20
213.  Demonstration System
22
23The ThreadX demonstration is designed to execute under the Keil debugger on the
24FVP_MPS2_Cortex-M33_MDK simulator.
25
26Building the demonstration is easy; simply select the "Batch Build" button.
27You should now observe the compilation and assembly of the ThreadX demonstration of
28both the demo_secure_zone and demo_threadx_non-secure_zone projects.
29Then click the Start/Stop Debug Session button to start the simulator and begin debugging.
30You are now ready to execute the ThreadX demonstration.
31
32
334.  System Initialization
34
35The entry point in ThreadX for the Cortex-M33 using AC6 tools uses the standard AC6
36Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized.
37
38The ThreadX tx_initialize_low_level.s file is responsible for setting up
39various system data structures, the vector area, and a periodic timer interrupt
40source.
41
42In addition, _tx_initialize_low_level determines the first available
43address for use by the application, which is supplied as the sole input
44parameter to your application definition function, tx_application_define.
45
46
475.  Register Usage and Stack Frames
48
49The following defines the saved context stack frames for context switches
50that occur as a result of interrupt handling or from thread-level API calls.
51All suspended threads have the same stack frame in the Cortex-M33 version of
52ThreadX. The top of the suspended thread's stack is pointed to by
53tx_thread_stack_ptr in the associated thread control block TX_THREAD.
54
55Non-FPU Stack Frame:
56
57    Stack Offset    Stack Contents
58
59    0x00            LR          Interrupted LR (LR at time of PENDSV)
60    0x04            r4          Software stacked GP registers
61    0x08            r5
62    0x0C            r6
63    0x10            r7
64    0x14            r8
65    0x18            r9
66    0x1C            r10
67    0x20            r11
68    0x24            r0          Hardware stacked registers
69    0x28            r1
70    0x2C            r2
71    0x30            r3
72    0x34            r12
73    0x38            lr
74    0x3C            pc
75    0x40            xPSR
76
77FPU Stack Frame (only interrupted thread with FPU enabled):
78
79    Stack Offset    Stack Contents
80
81    0x00            LR          Interrupted LR (LR at time of PENDSV)
82    0x04            s16         Software stacked FPU registers
83    0x08            s17
84    0x0C            s18
85    0x10            s19
86    0x14            s20
87    0x18            s21
88    0x1C            s22
89    0x20            s23
90    0x24            s24
91    0x28            s25
92    0x2C            s26
93    0x30            s27
94    0x34            s28
95    0x38            s29
96    0x3C            s30
97    0x40            s31
98    0x44            r4          Software stacked registers
99    0x48            r5
100    0x4C            r6
101    0x50            r7
102    0x54            r8
103    0x58            r9
104    0x5C            r10
105    0x60            r11
106    0x64            r0          Hardware stacked registers
107    0x68            r1
108    0x6C            r2
109    0x70            r3
110    0x74            r12
111    0x78            lr
112    0x7C            pc
113    0x80            xPSR
114    0x84            s0          Hardware stacked FPU registers
115    0x88            s1
116    0x8C            s2
117    0x90            s3
118    0x94            s4
119    0x98            s5
120    0x9C            s6
121    0xA0            s7
122    0xA4            s8
123    0xA8            s9
124    0xAC            s10
125    0xB0            s11
126    0xB4            s12
127    0xB8            s13
128    0xBC            s14
129    0xC0            s15
130    0xC4            fpscr
131
132
1336.  Improving Performance
134
135To make ThreadX and the application(s) run faster, you can enable
136all compiler optimizations.
137
138In addition, you can eliminate the ThreadX basic API error checking by
139compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
140defined.
141
142
1437.  Interrupt Handling
144
145ThreadX provides complete and high-performance interrupt handling for Cortex-M33
146targets. There are a certain set of requirements that are defined in the
147following sub-sections:
148
149
1507.1  Vector Area
151
152The Cortex-M33 vectors start at the label __Vectors or similar. The application may modify
153the vector area according to its needs. There is code in tx_initialize_low_level() that will
154configure the vector base register.
155
156
1577.2 Managed Interrupts
158
159ISRs can be written completely in C (or assembly language) without any calls to
160_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
161ThreadX API that is available to ISRs.
162
163ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
164
165void    your_C_isr(void)
166{
167
168    /* ISR processing goes here, including any needed function calls.  */
169}
170
171ISRs written in assembly language will take the form:
172
173
174    .global  your_assembly_isr
175    .thumb_func
176your_assembly_isr:
177; VOID your_assembly_isr(VOID)
178; {
179    PUSH    {r0, lr}
180;
181;    /* Do interrupt handler work here */
182;    /* BL <your interrupt routine in C> */
183
184    POP     {r0, lr}
185    BX      lr
186; }
187
188Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set.
189To accomplish this, the declaration of the label has to be preceded by the assembler directive
190.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
191be inserted in the correct location in the interrupt vector table. This table is typically
192located in either your runtime startup file or in the tx_initialize_low_level.s file.
193
194
1958. FPU Support
196
197ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads
198can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
199context.
200
201
2029.  Revision History
203
204For generic code revision information, please refer to the readme_threadx_generic.txt
205file, which is included in your distribution. The following details the revision
206information associated with this specific port of ThreadX:
207
20806-02-2021  Release 6.1.7 changes:
209            tx_port.h                           Remove unneeded include file
210            tx_thread_secure_stack_initialize.S New file
211            tx_thread_schedule.S                Added secure stack initialize to SVC hander
212            tx_thread_secure_stack.c            Fixed stack pointer save, initialize in handler mode
213
21404-02-2021  Release 6.1.6 changes:
215            tx_port.h                           Updated macro definition
216            tx_thread_schedule.s                Added low power support
217
21803-02-2021  The following files were changed/added for version 6.1.5:
219            tx_port.h                       Added ULONG64_DEFINED
220
22109-30-2020  Initial ThreadX 6.1 version for Cortex-M33 using AC6 tools.
222
223
224Copyright(c) 1996-2020 Microsoft Corporation
225
226
227https://azure.com/rtos
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229