1                     Microsoft's Azure RTOS ThreadX for Cortex-M3
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3                               Thumb & 32-bit Mode
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5                    Using the Keil Microcontroller Development Kit
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71.  Building the ThreadX run-time Library
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9Building the ThreadX library is easy, simply load the project file
10ThreadX_Library.Uv2, which is located inside the "example_build" directory.
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12Once the ThreadX library files are displayed in the project window,
13select the "Build Target" operation and observe the compilation and assembly
14of the ThreadX library. This project build produces the ThreadX library
15file ThreadX_Library.lib.
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17
182.  Demonstration System
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20The ThreadX demonstration is designed to execute under the Keil simulator or
21Cortex-M3 hardware. This demonstration is slightly smaller than typical ThreadX
22demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM.
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24Building the demonstration is easy; simply open the ThreadX demonstration
25project file ThreadX_Demo.Uv2, which is located inside the "example_build"
26directory.
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28Once open, select the "Build Target" operation and observe the compilation of
29sample_threadx.c (which is the demonstration application) and linking with
30ThreadX_Library.lib. The resulting file ThreadX_Demo.axf is a binary file that
31can be downloaded and executed under the uVision simulator or Cortex-M3 hardware.
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33For simulator execution, the following memory regions need to be defined via
34the "Debug -> Memory Map" dialog:
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360x20000000, 0x20080000 [check read and write access]
370xE0000000, 0xE8000000 [check read and write access]
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39
403.  System Initialization
41
42The entry point in ThreadX for the Cortex-M3 using Keil tools is at label
43__main. This is defined within the Keil compiler's startup code. In
44addition, this is where all static and global pre-set C variable
45initialization processing takes place.
46
47The ThreadX tx_initialize_low_level.s file is responsible for setting up
48various system data structures, the vector area, and a periodic timer interrupt
49source.
50
51In addition, _tx_initialize_low_level determines the first available
52address for use by the application, which is supplied as the sole input
53parameter to your application definition function, tx_application_define.
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564.  Register Usage and Stack Frames
57
58The following defines the saved context stack frames for context switches
59that occur as a result of interrupt handling or from thread-level API calls.
60All suspended threads have the same stack frame in the Cortex-M3 version of
61ThreadX. The top of the suspended thread's stack is pointed to by
62tx_thread_stack_ptr in the associated thread control block TX_THREAD.
63
64
65  Stack Offset     Stack Contents
66
67     0x00               r4
68     0x04               r5
69     0x08               r6
70     0x0C               r7
71     0x10               r8
72     0x14               r9
73     0x18               r10
74     0x1C               r11
75     0x20               r0          (Hardware stack starts here!!)
76     0x24               r1
77     0x28               r2
78     0x2C               r3
79     0x30               r12
80     0x34               lr
81     0x38               pc
82     0x3C               xPSR
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84
855.  Improving Performance
86
87The distribution version of ThreadX is built without any compiler
88optimizations. This makes it easy to debug because you can trace or set
89breakpoints inside of ThreadX itself. Of course, this costs some
90performance. To make it run faster, you can change the ThreadX_Library.Uv2
91project to debugging and enable all compiler optimizations.
92
93In addition, you can eliminate the ThreadX basic API error checking by
94compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
95defined.
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986.  Interrupt Handling
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100ThreadX provides complete and high-performance interrupt handling for Cortex-M3
101targets. There are a certain set of requirements that are defined in the
102following sub-sections:
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104
1056.1  Vector Area
106
107The Cortex-M3 vectors start at the label __tx_vectors. The application may modify
108the vector area according to its needs.
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110
1116.2 Managed Interrupts
112
113ISRs for Cortex-M can be written completely in C (or assembly language) without any
114calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
115access to the ThreadX API that is available to ISRs.
116
117ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
118
119void    your_C_isr(void)
120{
121
122    /* ISR processing goes here, including any needed function calls.  */
123}
124
125ISRs written in assembly language will take the form:
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127    EXPORT  your_assembly_isr
128your_assembly_isr
129
130    PUSH    {r0, lr}
131
132    ; ISR processing goes here, including any needed function calls.
133
134    POP     {r0, lr}
135    BX      lr
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1397.  Revision History
140
141For generic code revision information, please refer to the readme_threadx_generic.txt
142file, which is included in your distribution. The following details the revision
143information associated with this specific port of ThreadX:
144
14504-02-2021  Release 6.1.6 changes:
146            tx_port.h                           Updated macro definition
147            tx_thread_schedule.s                Fix compilation error
148
14903-02-2021  The following files were changed/added for version 6.1.5:
150            tx_thread_schedule.s            Added low power feature
151
15209-30-2020  Initial ThreadX 6.1 version for Cortex-M3 using Keil tools.
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155Copyright(c) 1996-2020 Microsoft Corporation
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158https://azure.com/rtos
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