1                     Microsoft's Azure RTOS ThreadX for Cortex-M0
2
3                            Using ARM Compiler 5 (AC5)
4
51.  Building the ThreadX run-time Library
6
7First make sure you are in the "example_build" directory. Also, make sure that
8you have setup your path and other environment variables necessary for the AC5
9development environment. At this point you may run the build_threadx.bat batch
10file. This will build the ThreadX run-time environment in the "example_build"
11directory.
12
13You should observe assembly and compilation of a series of ThreadX source
14files. At the end of the batch file, they are all combined into the
15run-time library file: tx.a. This file must be linked with your
16application in order to use ThreadX.
17
18
192.  Demonstration System
20
21The ThreadX demonstration is designed to execute under the ARM
22Windows-based simulator.
23
24Building the demonstration is easy; simply execute the build_threadx_sample.bat
25batch file while inside the "example_build" directory.
26
27You should observe the compilation of sample_threadx.c (which is the demonstration
28application) and linking with tx.a. The resulting file sample_threadx.axf
29is a binary file that can be downloaded and executed on the ARM simulator.
30
31
323.  System Initialization
33
34The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label
35__main. This is defined within the AC5 compiler's startup code. In
36addition, this is where all static and global pre-set C variable
37initialization processing takes place.
38
39The ThreadX tx_initialize_low_level.s file is responsible for setting up
40various system data structures, the vector area, and a periodic timer interrupt
41source.
42
43In addition, _tx_initialize_low_level determines the first available
44address for use by the application, which is supplied as the sole input
45parameter to your application definition function, tx_application_define.
46
47
484.  Register Usage and Stack Frames
49
50The following defines the saved context stack frames for context switches
51that occur as a result of interrupt handling or from thread-level API calls.
52All suspended threads have the same stack frame in the Cortex-M0 version of
53ThreadX. The top of the suspended thread's stack is pointed to by
54tx_thread_stack_ptr in the associated thread control block TX_THREAD.
55
56
57  Stack Offset     Stack Contents
58
59     0x00               r8
60     0x04               r9
61     0x08               r10
62     0x0C               r11
63     0x10               r4
64     0x14               r5
65     0x18               r6
66     0x1C               r7
67     0x20               r0          (Hardware stack starts here!!)
68     0x24               r1
69     0x28               r2
70     0x2C               r3
71     0x30               r12
72     0x34               lr
73     0x38               pc
74     0x3C               xPSR
75
76
775.  Improving Performance
78
79The distribution version of ThreadX is built without any compiler
80optimizations. This makes it easy to debug because you can trace or set
81breakpoints inside of ThreadX itself. Of course, this costs some
82performance. To make it run faster, you can change the build_threadx.bat file to
83remove the -g option and enable all compiler optimizations.
84
85In addition, you can eliminate the ThreadX basic API error checking by
86compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
87defined.
88
89
906.  Interrupt Handling
91
92ThreadX provides complete and high-performance interrupt handling for Cortex-M0
93targets. There are a certain set of requirements that are defined in the
94following sub-sections:
95
96
976.1  Vector Area
98
99The Cortex-M0 vectors start at the label __tx_vectors. The application may modify
100the vector area according to its needs.
101
1026.2 Managed Interrupts
103
104ISRs for Cortex-M can be written completely in C (or assembly language) without any
105calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
106access to the ThreadX API that is available to ISRs.
107
108ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
109
110void    your_C_isr(void)
111{
112
113    /* ISR processing goes here, including any needed function calls.  */
114}
115
116ISRs written in assembly language will take the form:
117
118    EXPORT  your_assembly_isr
119your_assembly_isr
120
121    PUSH    {r0, lr}
122
123    ; ISR processing goes here, including any needed function calls.
124
125    POP     {r0, r1}
126    MOV     lr, r1
127    BX      lr
128
129
1307.  Revision History
131
132For generic code revision information, please refer to the readme_threadx_generic.txt
133file, which is included in your distribution. The following details the revision
134information associated with this specific port of ThreadX:
135
13604-02-2021  Release 6.1.6 changes:
137            tx_port.h                           Updated macro definition
138            tx_thread_schedule.s                Fix compilation error
139
14003-02-2021  The following files were changed/added for version 6.1.5:
141            tx_thread_schedule.s            Added low power feature
142
14309-30-2020  Initial ThreadX 6.1 version for Cortex-M0 using AC5 tools.
144
145
146Copyright(c) 1996-2020 Microsoft Corporation
147
148
149https://azure.com/rtos
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