1 Microsoft's Azure RTOS ThreadX for Cortex-A35 2 3 Using the ARM Compiler 6 & DS 4 51. Import the ThreadX Projects 6 7In order to build the ThreadX library and the ThreadX SMP demonstration, first import 8the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) 9into your DS workspace. 10 11 122. Building the ThreadX run-time Library 13 14Building the ThreadX library is easy; simply select the Eclipse project file 15"tx" and then select the build button. You should now observe the compilation 16and assembly of the ThreadX library. This project build produces the ThreadX 17library file tx.a. 18 19 203. Demonstration System 21 22The ThreadX demonstration is designed to execute under the DS debugger on the 23Base_A35x1 Bare Metal simulator. 24 25Building the demonstration is easy; simply select the sample_threadx project, and 26select the build button. Next, in the sample_threadx project, right-click on the 27sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is 28setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load 29the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute 30the ThreadX SMP demonstration. 31 32 334. System Initialization 34 35The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label 36start64. This is defined within the AC6 compiler's startup code. In addition, 37this is where all static and global pre-set C variable initialization processing 38takes place. 39 40The ThreadX tx_initialize_low_level.s file is responsible for determining the 41first available RAM address for use by the application, which is supplied as the 42sole input parameter to your application definition function, tx_application_define. 43 44 455. Register Usage and Stack Frames 46 47The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers 48for each function. All other registers used by a C function must be preserved 49by the function. ThreadX takes advantage of this in situations where a context 50switch happens as a result of making a ThreadX service call (which is itself a 51C function). In such cases, the saved context of a thread is only the 52non-scratch registers. 53 54The following defines the saved context stack frames for context switches 55that occur as a result of interrupt handling or from thread-level API calls. 56All suspended threads have one of these two types of stack frames. The top 57of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 58associated thread control block TX_THREAD. 59 60 61FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 62 63 Offset Interrupted Stack Frame Non-Interrupt Stack Frame 64 65 0x000 SPSR DAIF 66 0x008 ELR 0 67 0x010 x28 x27 68 0x018 reserved x28 69 0x020 x26 x25 70 0x028 x27 x26 71 0x030 x24 x23 72 0x038 x25 x24 73 0x040 x22 x21 74 0x048 x23 x22 75 0x050 x20 x19 76 0x058 x21 x20 77 0x060 x18 x29 78 0x068 x19 x30 79 0x070 x16 80 0x078 x17 81 0x080 x14 82 0x088 x15 83 0x090 x12 84 0x098 x13 85 0x0A0 x10 86 0x0A8 x11 87 0x0B0 x8 88 0x0B8 x9 89 0x0C0 x6 90 0x0C8 x7 91 0x0D0 x4 92 0x0D8 x5 93 0x0E0 x2 94 0x0E8 x3 95 0x0F0 x0 96 0x0F8 x1 97 0x100 x29 98 0x108 x30 99 100 101FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 102 103 Offset Interrupted Stack Frame Non-Interrupt Stack Frame 104 105 0x000 SPSR DAIF 106 0x008 ELR 0 107 0x010 FPSR FPSR 108 0x018 FPCR FPCR 109 0x020 q30 q14 110 0x030 q31 q15 111 0x040 q28 q12 112 0x050 q29 q13 113 0x060 q26 q10 114 0x070 q27 q11 115 0x080 q24 q8 116 0x090 q25 q9 117 0x0A0 q22 x27 118 0x0A8 x28 119 0x0B0 q23 x25 120 0x0B8 x26 121 0x0C0 q20 x23 122 0x0C8 x24 123 0x0D0 q21 x21 124 0x0D8 x22 125 0x0E0 q18 x19 126 0x0E8 x20 127 0x0F0 q19 x29 128 0x0F8 x30 129 0x100 q16 130 0x110 q17 131 0x120 q14 132 0x130 q15 133 0x140 q12 134 0x150 q13 135 0x160 q10 136 0x170 q11 137 0x180 q8 138 0x190 q9 139 0x1A0 q6 140 0x1B0 q7 141 0x1C0 q4 142 0x1D0 q5 143 0x1E0 q2 144 0x1F0 q3 145 0x200 q0 146 0x210 q1 147 0x220 x28 148 0x228 reserved 149 0x230 x26 150 0x238 x27 151 0x240 x24 152 0x248 x25 153 0x250 x22 154 0x258 x23 155 0x260 x20 156 0x268 x21 157 0x270 x18 158 0x278 x19 159 0x280 x16 160 0x288 x17 161 0x290 x14 162 0x298 x15 163 0x2A0 x12 164 0x2A8 x13 165 0x2B0 x10 166 0x2B8 x11 167 0x2C0 x8 168 0x2C8 x9 169 0x2D0 x6 170 0x2D8 x7 171 0x2E0 x4 172 0x2E8 x5 173 0x2F0 x2 174 0x2F8 x3 175 0x300 x0 176 0x308 x1 177 0x310 x29 178 0x318 x30 179 180 181 1826. Improving Performance 183 184The distribution version of ThreadX is built without any compiler optimizations. 185This makes it easy to debug because you can trace or set breakpoints inside of 186ThreadX itself. Of course, this costs some performance. To make it run faster, 187you can change the project settings to the desired compiler optimization level. 188 189In addition, you can eliminate the ThreadX basic API error checking by 190compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 191defined. 192 193 1947. Interrupt Handling 195 196ThreadX provides complete and high-performance interrupt handling for Cortex-A35 197targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following 198format: 199 200 .global irq_handler 201irq_handler: 202 MSR SPSel, 0 203 STP x29, x30, [sp, #-16]! 204 BL _tx_thread_context_save 205 206 /* Your ISR call goes here! */ 207 BL application_isr_handler 208 209 B _tx_thread_context_restore 210 211By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 212and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 213 214 2158. ThreadX Timer Interrupt 216 217ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, 218timeouts, and application timers. Without such a timer interrupt source, these services 219are not functional. However, all other ThreadX services are operational without a 220periodic timer source. 221 222 2239. ARM FP Support 224 225By default, FP support is disabled for each thread. If saving the context of the FP registers 226is needed, the following API call must be made from the context of the application thread - before 227the FP usage: 228 229void tx_thread_fp_enable(void); 230 231After this API is called in the application, FP registers will be saved/restored for this thread if it 232is preempted via an interrupt. All other suspension of the this thread will not require the FP registers 233to be saved/restored. 234 235To disable FP register context saving, simply call the following API: 236 237void tx_thread_fp_disable(void); 238 239 24010. Revision History 241 242For generic code revision information, please refer to the readme_threadx_generic.txt 243file, which is included in your distribution. The following details the revision 244information associated with this specific port of ThreadX: 245 24604-02-2021 Release 6.1.6 changes: 247 tx_port.h Updated macro definition 248 24909-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools. 250 251 252Copyright(c) 1996-2020 Microsoft Corporation 253 254 255https://azure.com/rtos 256 257
