1@/*************************************************************************** 2@ * Copyright (c) 2024 Microsoft Corporation 3@ * 4@ * This program and the accompanying materials are made available under the 5@ * terms of the MIT License which is available at 6@ * https://opensource.org/licenses/MIT. 7@ * 8@ * SPDX-License-Identifier: MIT 9@ **************************************************************************/ 10@ 11@ 12@/**************************************************************************/ 13@/**************************************************************************/ 14@/** */ 15@/** ThreadX Component */ 16@/** */ 17@/** Thread */ 18@/** */ 19@/**************************************************************************/ 20@/**************************************************************************/ 21#ifdef TX_INCLUDE_USER_DEFINE_FILE 22#include "tx_user.h" 23#endif 24 25FIQ_DISABLE = 0x40 @ FIQ disable bit 26MODE_MASK = 0x1F @ Mode mask 27SYS_MODE_BITS = 0x1F @ System mode bits 28@ 29@ 30@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start 31@ since it will never be called 16-bit mode. */ 32@ 33 .arm 34 .text 35 .align 2 36@/**************************************************************************/ 37@/* */ 38@/* FUNCTION RELEASE */ 39@/* */ 40@/* _tx_thread_fiq_nesting_start ARM11/GNU */ 41@/* 6.2.1 */ 42@/* AUTHOR */ 43@/* */ 44@/* William E. Lamie, Microsoft Corporation */ 45@/* */ 46@/* DESCRIPTION */ 47@/* */ 48@/* This function is called by the application from FIQ mode after */ 49@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ 50@/* processing to the system mode so nested FIQ interrupt processing */ 51@/* is possible (system mode has its own "lr" register). Note that */ 52@/* this function assumes that the system mode stack pointer was setup */ 53@/* during low-level initialization (tx_initialize_low_level.s). */ 54@/* */ 55@/* This function returns with FIQ interrupts enabled. */ 56@/* */ 57@/* INPUT */ 58@/* */ 59@/* None */ 60@/* */ 61@/* OUTPUT */ 62@/* */ 63@/* None */ 64@/* */ 65@/* CALLS */ 66@/* */ 67@/* None */ 68@/* */ 69@/* CALLED BY */ 70@/* */ 71@/* ISRs */ 72@/* */ 73@/* RELEASE HISTORY */ 74@/* */ 75@/* DATE NAME DESCRIPTION */ 76@/* */ 77@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 78@/* 03-08-2023 Cindy Deng Modified comment(s), added */ 79@/* #include tx_user.h, */ 80@/* resulting in version 6.2.1 */ 81@/* */ 82@/**************************************************************************/ 83@VOID _tx_thread_fiq_nesting_start(VOID) 84@{ 85 .global _tx_thread_fiq_nesting_start 86 .type _tx_thread_fiq_nesting_start,function 87_tx_thread_fiq_nesting_start: 88 MOV r3,lr @ Save ISR return address 89 MRS r0, CPSR @ Pickup the CPSR 90 BIC r0, r0, #MODE_MASK @ Clear the mode bits 91 ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR 92 MSR CPSR_cxsf, r0 @ Enter system mode 93 STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack 94 @ and push r1 just to keep 8-byte alignment 95 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR 96 MSR CPSR_cxsf, r0 @ Enter system mode 97 MOV pc, r3 @ Return to caller 98@} 99 100