1;/*************************************************************************** 2; * Copyright (c) 2024 Microsoft Corporation 3; * 4; * This program and the accompanying materials are made available under the 5; * terms of the MIT License which is available at 6; * https://opensource.org/licenses/MIT. 7; * 8; * SPDX-License-Identifier: MIT 9; **************************************************************************/ 10; 11; 12;/**************************************************************************/ 13;/**************************************************************************/ 14;/** */ 15;/** ThreadX Component */ 16;/** */ 17;/** Thread */ 18;/** */ 19;/**************************************************************************/ 20;/**************************************************************************/ 21; 22; 23;#define TX_SOURCE_CODE 24; 25; 26;/* Include necessary system files. */ 27; 28;#include "tx_api.h" 29;#include "tx_thread.h" 30; 31; 32SVC_MODE EQU 0x13 ; SVC mode 33 IF :DEF:TX_ENABLE_FIQ_SUPPORT 34CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled 35 ELSE 36CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled 37 ENDIF 38; 39; 40 AREA ||.text||, CODE, READONLY 41;/**************************************************************************/ 42;/* */ 43;/* FUNCTION RELEASE */ 44;/* */ 45;/* _tx_thread_stack_build ARM11/AC5 */ 46;/* 6.1 */ 47;/* AUTHOR */ 48;/* */ 49;/* William E. Lamie, Microsoft Corporation */ 50;/* */ 51;/* DESCRIPTION */ 52;/* */ 53;/* This function builds a stack frame on the supplied thread's stack. */ 54;/* The stack frame results in a fake interrupt return to the supplied */ 55;/* function pointer. */ 56;/* */ 57;/* INPUT */ 58;/* */ 59;/* thread_ptr Pointer to thread control blk */ 60;/* function_ptr Pointer to return function */ 61;/* */ 62;/* OUTPUT */ 63;/* */ 64;/* None */ 65;/* */ 66;/* CALLS */ 67;/* */ 68;/* None */ 69;/* */ 70;/* CALLED BY */ 71;/* */ 72;/* _tx_thread_create Create thread service */ 73;/* */ 74;/* RELEASE HISTORY */ 75;/* */ 76;/* DATE NAME DESCRIPTION */ 77;/* */ 78;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 79;/* */ 80;/**************************************************************************/ 81;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) 82;{ 83 EXPORT _tx_thread_stack_build 84_tx_thread_stack_build 85; 86; 87; /* Build a fake interrupt frame. The form of the fake interrupt stack 88; on the ARM11 should look like the following after it is built: 89; 90; Stack Top: 1 Interrupt stack frame type 91; CPSR Initial value for CPSR 92; a1 (r0) Initial value for a1 93; a2 (r1) Initial value for a2 94; a3 (r2) Initial value for a3 95; a4 (r3) Initial value for a4 96; v1 (r4) Initial value for v1 97; v2 (r5) Initial value for v2 98; v3 (r6) Initial value for v3 99; v4 (r7) Initial value for v4 100; v5 (r8) Initial value for v5 101; sb (r9) Initial value for sb 102; sl (r10) Initial value for sl 103; fp (r11) Initial value for fp 104; ip (r12) Initial value for ip 105; lr (r14) Initial value for lr 106; pc (r15) Initial value for pc 107; 0 For stack backtracing 108; 109; Stack Bottom: (higher memory address) */ 110; 111 LDR r2, [r0, #16] ; Pickup end of stack area 112 BIC r2, r2, #7 ; Ensure 8-byte alignment 113 SUB r2, r2, #76 ; Allocate space for the stack frame 114; 115; /* Actually build the stack frame. */ 116; 117 MOV r3, #1 ; Build interrupt stack type 118 STR r3, [r2, #0] ; Store stack type 119 MOV r3, #0 ; Build initial register value 120 STR r3, [r2, #8] ; Store initial r0 121 STR r3, [r2, #12] ; Store initial r1 122 STR r3, [r2, #16] ; Store initial r2 123 STR r3, [r2, #20] ; Store initial r3 124 STR r3, [r2, #24] ; Store initial r4 125 STR r3, [r2, #28] ; Store initial r5 126 STR r3, [r2, #32] ; Store initial r6 127 STR r3, [r2, #36] ; Store initial r7 128 STR r3, [r2, #40] ; Store initial r8 129 STR r3, [r2, #44] ; Store initial r9 130 LDR r3, [r0, #12] ; Pickup stack starting address 131 STR r3, [r2, #48] ; Store initial r10 (sl) 132 MOV r3, #0 ; Build initial register value 133 STR r3, [r2, #52] ; Store initial r11 134 STR r3, [r2, #56] ; Store initial r12 135 STR r3, [r2, #60] ; Store initial lr 136 STR r1, [r2, #64] ; Store initial pc 137 STR r3, [r2, #68] ; 0 for back-trace 138 MRS r1, CPSR ; Pickup CPSR 139 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR 140 ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled 141 STR r3, [r2, #4] ; Store initial CPSR 142; 143; /* Setup stack pointer. */ 144; thread_ptr -> tx_thread_stack_ptr = r2; 145; 146 STR r2, [r0, #8] ; Save stack pointer in thread's 147 ; control block 148 IF {INTER} = {TRUE} 149 BX lr ; Return to caller 150 ELSE 151 MOV pc, lr ; Return to caller 152 ENDIF 153;} 154 END 155 156
